AI hardware news: chips, optics and the compute supply chain
Track AI chips, memory, lithography, semiconductor equipment, optics, advanced packaging, PCBs, servers, power, cooling and edge devices. Explore specifications, supply and demand, with original sources and publication times.
Semiconductor fabs are using real-time equipment sensor data and AI/ML inference models to move yield anomaly detection inside process modules, accelerating yield learning and improving advanced process control (APC). Equipment sensor sampling has risen from about once per second to once every few tens of milliseconds, data types have grown at least 10x compared with a decade ago, and some fabs generate hundreds of petabytes per year. How to process data in sub-second timescales while preserving context and connectivity is the main data management challenge shift left brings.
Every test, inspection and monitoring method for advanced chips has physical, spatial or temporal blind spots, and no single technology provides a complete picture. Vendors including Nordson, ZEISS and Teradyne note that defects such as solder voids and head-in-pillow can pass electrical test yet cause early failures, while X-ray still faces trade-offs among precision, throughput and resolution for stacked dies and TSV inspection.
In advanced packaging, defects accumulate value step by step through the process flow, and shrinking feature sizes push inspection requirements toward front-end levels, spanning surface particles, sidewall cracks, buried defects, microbump anomalies and bonding voids. Manufacturers need to combine complementary methods—high-sensitivity 2D inspection, infrared subsurface inspection and 3D metrology—in a unified workflow, balancing sensitivity with throughput, and use effective classification to turn inspection results into actionable process information.
Microsoft held a Windows and Surface event in San Francisco, announcing that the Surface Laptop Ultra with NVIDIA's Arm-based RTX Spark chip will go on sale October 16.
Researchers at Carl Zeiss SMT and ASML published a paper proposing a Hyper-NA EUV lithography scheme with a numerical aperture of at least 0.75, as a path beyond today's 0.55 NA High-NA systems.
NVIDIA and Microsoft announced at the Windows AI and Surface event in San Francisco that they are jointly building agent software and hardware for Windows PCs.
Why it matters: The article details the specs and launch timeline for RTX Spark and DGX Station for Windows, helping readers assess how realistic running large models locally with resident agents will be.
Oct 7Wed
Wednesday
Semiconductor Engineering Chips and PackagingAI score4747
imec is advancing its CFET device roadmap, projecting that the industry may shift to CFET architectures from the A7 logic node, shrinking standard cells to 4.5-track and below.
Semiconductor Engineering rounds up this week's blogs: a Siemens team explores how CFETs and buried power rails can shrink chip area and improve energy efficiency to meet the needs of AI accelerators, data centers, and mobile processors; Synopsys and Cadence analyze the collaborative advantages of agentic AI in EDA; Arm introduces the AMBA C2C extension for chiplet connectivity.
Precisely aligning and fixing fiber array units—FAU coupling—has become a critical bottleneck in CPO manufacturing and testing. At SEMICON Taiwan 2026, TSMC unveiled an upgraded COUPE roadmap: per-chip bandwidth reaching 3.2 Tbps in 2026, doubling to 6.4 Tbps in 2027, with a long-term target exceeding 51.2 Tbps. Integrating optics on the substrate can deliver a 4X power-efficiency gain, with OOI reaching 10X.
AMD has released video resources related to AMD Helios AI infrastructure, along with brand assets including AMD trademarks and logos for download. Before downloading, users must accept terms and conditions: these AMD Marks may only be used in promotional materials featuring products with AMD CPUs, GPUs, APUs or FPGAs, and AMD may terminate the license at any time.
AMD is sampling the Versal AI Core adaptive SoC in an enhanced space-grade package aimed at the most demanding space missions. The page's body is only licensing terms for AMD trademarks and brand asset downloads, with no specifics on chip parameters, performance or availability.
Using SEMulator3D digital twin modeling, Lam Research validated a self-aligned complementary field-effect transistor (SA-CFET) architecture that could extend CMOS scaling beyond the 10-angstrom node.
Lam Research has opened its largest US warehouse in Livermore, California—a 470,000-square-foot logistics and supply chain hub built to support semiconductor supply chain pressures driven by AI technology demand. A 40,000-square-foot automated storage and retrieval system with 15 robots cuts parts retrieval time from 6 minutes to under 30 seconds, 12 times faster than the existing system. The center is expected to support more than 200 jobs by 2027.
At the TSMC OIP Conference held in Santa Clara, California, SK hynix showcased its next-generation memory portfolio and won the Partner of the Year award (3DFabric-HBM Integration category) for the second consecutive year.
TrendForce has observed that some cloud service providers are adding QLC SSDs to SSD PODs, replacing the default TLC SSD plus HDD configuration. In AI inference, the Prefill and Decode stages repeatedly read and write KV Cache, and as context windows and batch sizes grow, KV Cache capacity needs multiply, prompting vendors to move caching from costly, capacity-limited HBM down to cheaper tiers.
AMD released an "Advanced Insights" video explaining how the Zen architecture is evolving for the agentic AI era. The page contains only AMD brand asset download terms, with no specific technical details or data on the architecture's evolution.
Marvell will present industry-first 2nm optical interconnect demonstrations at ECOC 2026 in Malaga, Spain, September 20–24, 2026, including the first 2nm 400G/lane optical PAM4, the first 2nm 800G ZR/ZR+ pluggable modules with MACsec (driven by the Libra 2nm coherent DSP), and the first 2nm 1.6T ZR and coherent-lite O-band demos.
SK hynix took part in AI Infra Summit 2026, held September 15–17 in Santa Clara, USA, presenting next-generation AI memory solutions under the theme "New Spectrum." Attendance was about 6,000, double the previous year.
At the AI Infra Summit, AMD argued that the core of AI infrastructure design should not be chips or networking but a system's ability to adapt to changing demands. The piece notes that agentic AI turns a single request into a multi-step chain of retrieval, tool calls, code execution and sub-agent coordination, and should be measured by cost per completed task rather than cost per token, offering three auditable principles: adaptable, economical, and open.
TrendForce says 4hi HBM samples will enter supplier views in early 3Q26, with NVIDIA and other AI chip vendors evaluating low-stack configurations to cope with the HBM shortage. The spec has real use cases in edge AI scenarios like autonomous driving and robotics; SK hynix previously supplied HBM2E to Waymo in 2024 with automotive certification, but near-term demand contribution remains very low.
TrendForce takes a deep dive into 3D advanced packaging and hybrid bonding: TSMC's SoIC uses 3D interconnect with 56x the interconnect density and 5x the energy efficiency of CoWoS, entered mass production in 2025 with a 6µm bond pitch, and plans to shrink to 4.5µm by 2029; Intel's Foveros Direct, at a 9µm pitch, enters mass production in 1H26 with the Clearwater Forest Xeon 6+.
Marvell announced it will showcase its AI data center connectivity and storage solution portfolio at AI Infra Summit 2026 (September 15–17, Santa Clara Convention Center, Booth #704).
AI's demand for larger, more complex chip packaging is pushing the industry to explore panel-level packaging (PLP): replacing round wafers with rectangular panels to improve area utilization and scalability beyond traditional wafer-level packaging size limits. Lam Research is advancing the technology toward production readiness through tool innovation and infrastructure investments, including the Salzburg Panel Center of Excellence. The technology still faces challenges in uniformity control, yield management, and industry standards.
At the SPIE Photomask and EUV Lithography conference, Intel Foundry and ASML reported progress on High NA EUV volume readiness; the technology has already been used in production of some Core Ultra Series 3 (Panther Lake) processors on Intel's 18A process.
AMD claims that 14 EPYC 9965 servers can replace 100 dual-socket Intel Xeon Platinum 8280 servers aged 5-7 years, cutting server count by 86% while delivering the same total performance, reducing power consumption by 69% and three-year TCO by 41%.
TrendForce analyzes the data center expansion strategies of the five major CSPs—Amazon, Microsoft, Google, Meta, and Oracle—noting that their signed but not yet activated lease commitments total about $1.16 trillion.
Lam Research has broken ground on a new laboratory expansion at its R&D center in Tualatin, Oregon. Once complete, the facility will add 120,000 square feet, expanding cleanroom space by more than 50%, with operation expected in 2028.
AMD, Cisco and HUMAIN announced that AI infrastructure built on AMD Instinct MI355X GPUs, EPYC CPUs and Cisco Silicon One AI networking has officially gone live in Saudi Arabia, providing production-grade compute to HUMAIN customers, with plans to expand to 250 MW.
AMD announced that its Instinct GPUs and EPYC CPUs will provide the compute for Europe's next-generation LUMI-AI supercomputer. (The original article contains only AMD trademark download terms and provides no further technical details of the partnership.)
AMD, Cisco and HUMAIN announced that AI infrastructure based on AMD Instinct MI355X GPUs, AMD EPYC CPUs and Cisco Silicon One networking has gone live in Saudi Arabia, offering HUMAIN customers GPU-as-a-service from model training to inference, with plans to reach 1 GW by 2030.
On August 25, at Dell Technologies Forum 2026 (DTF) held at COEX in Seoul, SK hynix showcased an AI memory portfolio spanning the full memory hierarchy, continuing its collaboration with strategic partner Dell.
Lam Research used SEMulator3D® integrated stress modeling to predict stress non-uniformity across GAA stacked nanosheet channels before fabrication — nFET stress differences reach 400–800 MPa, while pFET stays below 200 MPa. DOE experiments show that channel thickness, fin width, and lateral etch jointly affect stress uniformity, with increasing the topmost channel thickness from 4 nm to 7 nm significantly reducing the stress difference.
AMD announced it will be first to offer native UCIe 1.1 interface support in Versal adaptive SoCs, enabling low-power, high-bandwidth communication between adaptive SoCs and co-packaged specialty chiplets.
TrendForce maps the latest landscape of 2.5D/3D advanced packaging in the AI chip supply chain: TSMC's 5.5x reticle CoWoS is in mass production with yields above 98%, with plans to expand beyond 14x after 2029; Intel's EMIB-T yields have improved significantly, expanding beyond 8x this year and over 12x by 2028, targeting customer mass production in 2027.
AMD announced that as of mid-2026 its AI energy efficiency improvement is estimated at 4x, exceeding the 3x expected for this phase, as it advances toward its 20x30 goal of a 20x improvement in rack-scale AI training and inference energy efficiency by 2030.
Marvell will showcase its AI memory and storage portfolio at FMS 2026 on August 4-6 at Booth #805, featuring PCIe 6.0 enterprise SSD controllers, CXL near-memory acceleration and memory pooling switches, CXL memory expansion cards, Octeon DPUs, and Photonic Fabric technology for optical interconnect scaling.
At Advancing AI 2026 on July 23, AMD unveiled a full-stack AI and physical AI product portfolio, including its first rackscale solution, AMD Helios (72 Instinct MI455X GPUs plus 18 6th Gen EPYC "Venice" CPUs).
Why it matters: The official announcement consolidates Helios rack, MI400 series CPU/GPU spec figures, and major customer deployment plans, allowing readers to benchmark actual progress against competing solutions.
Jul 22Wed
Wednesday
TrendForce Insights Semiconductor Industry InsightsAI score4646
As test-time scaling rises, the AI industry's focus is shifting from training to inference, bringing structural changes to the memory hierarchy. In the first half of 2026, NVIDIA and Google respectively launched CMX, Rubin integrated Groq LPX, and the TPU v8i designed for inference (with 72 GB more HBM3e and 384 MB SRAM than the TPU v8t).