The actual reach of a PCIe retimer is not set by the spec but by multiple factors including SerDes architecture, controller intelligence, channel quality, and diagnostics. PCI-SIG typically requires about 36 dB insertion loss tolerance, but leading vendors' retimers can tolerate 40 dB or more, enabling longer PCB traces, more connectors, and greater manufacturing variance. As PCIe Gen6 advances, designs beyond compliance testing, interoperability, and observability become key to real-world deployment reliability.
Marvell, Microsoft, and Oracle announced a new working group under the Open Compute Project (OCP) Security track, aiming to standardize integrated HSMs for cloud and hyperscale data centers at NIST FIPS 140-3 Level 3.
Marvell has launched its second-generation Structera X 3406 and 3506 CXL 3.2 memory expanders, built on an industry-first six-channel DDR4/DDR5 design that increases channel count by 50% over the previous generation, supports PCIe Gen 6, and allows a single controller to support up to 9TB DDR4 or 6TB DDR5.
AMD has launched the AMD Helion agentic AI rack, an open blueprint for agentic AI infrastructure designed to Open Compute Project specifications and powered by AMD compute.
Amazon says it will no longer use NDAs when negotiating data center deals with local governments, following a similar move by Microsoft earlier this year. Meanwhile, a wave of startups is betting consumers will let AI agents access their email, files and credit cards, while United, Apple and Amazon are putting up barriers to external agents.
Amazon says it will no longer use NDAs when negotiating data center deals with local governments, following a similar move by Microsoft earlier this year. The secrecy fueled community backlash against AI infrastructure, with hundreds of pause proposals or laws emerging from New York to San Francisco. TechCrunch’s Equity podcast also discusses why personal AI startups treat trust as the real product.
Ambrosia Energy CEO Ben Longmier and Bill Thayer, head of data center solutions at Bloom Energy, will sit down for a conversation titled “Where the AI infrastructure boom is creating winners” on the Smart Systems Stage at TechCrunch Disrupt 2026.
Ben Mitchel, senior director of Teradyne's Integrated System Test division, explains why system-level test has become critical for mass production of AI and data center equipment. These devices use multi-chiplet designs and draw thousands of watts, requiring testing under real-world conditions. The Titan HP platform delivers the power, thermal management, and throughput such devices demand.
TrendForce has observed that some cloud service providers are adding QLC SSDs to SSD PODs, replacing the default TLC SSD plus HDD configuration. In AI inference, the Prefill and Decode stages repeatedly read and write KV Cache, and as context windows and batch sizes grow, KV Cache capacity needs multiply, prompting vendors to move caching from costly, capacity-limited HBM down to cheaper tiers.
Marvell will present industry-first 2nm optical interconnect demonstrations at ECOC 2026 in Malaga, Spain, September 20–24, 2026, including the first 2nm 400G/lane optical PAM4, the first 2nm 800G ZR/ZR+ pluggable modules with MACsec (driven by the Libra 2nm coherent DSP), and the first 2nm 1.6T ZR and coherent-lite O-band demos.
TrendForce launched Weekly Radar, a free subscription column that tracks supply and lead times for six component categories—GPU, DRAM, NAND, HDD, ABF, and MLCC—each week. The first issue notes the GPU is the only one of the six with lead times at balanced levels, while ABF lead times are 48-56 weeks, far above the balanced 12 weeks.
During LEAP 2026, AMD announced that AI infrastructure built with Cisco and HUMAIN, based on AMD Instinct MI355X GPUs, EPYC CPUs and Cisco networking equipment, is now in production service, with plans to add up to 250 megawatts starting from 2027 and the joint venture on track to reach up to 1 gigawatt by 2030.
AMD claims that 14 EPYC 9965 servers can replace 100 dual-socket Intel Xeon Platinum 8280 servers aged 5-7 years, cutting server count by 86% while delivering the same total performance, reducing power consumption by 69% and three-year TCO by 41%.
Lam Research has broken ground on a new laboratory expansion at its R&D center in Tualatin, Oregon. Once complete, the facility will add 120,000 square feet, expanding cleanroom space by more than 50%, with operation expected in 2028.
AMD announced that as of mid-2026 its AI energy efficiency improvement is estimated at 4x, exceeding the 3x expected for this phase, as it advances toward its 20x30 goal of a 20x improvement in rack-scale AI training and inference energy efficiency by 2030.
AMD released its 2025-26 Corporate Responsibility Report, reviewing progress on 2020-2025 goals and looking ahead to 2030. From 2020 to 2025, renewable electricity rose from 22% to 58%, operational greenhouse gas emissions fell 30%, AI training and high-performance computing node energy efficiency improved 38x, and AMD systems on the Green500 list grew from 11 to 194; new targets include a 20x improvement in rack-scale AI energy efficiency from 2024 to 2030.
In the first half of 2026, the core constraint of AI inference has shifted from compute to memory, as surging KV Cache demands meet limited memory supply and become the main bottleneck. For Llama 3 70B FP16, model weights are about 140GiB, but the KV Cache reaches 160GiB at 64K context and balloons to 320GiB at 128K, about 2.3 times the weight size.
TrendForce analysis indicates that large-scale AI data center (AIDC) deployments in 2026 are pushing energy storage from an optional add-on to critical infrastructure. North America urgently needs storage to secure 24/7 power given gas generation's 40-50% share and tight supply of large gas turbines; China has made compute-power coordination part of new infrastructure, making 4-8 hour long-duration storage standard for compute hubs. AIDC storage is deployed on both the data center side and the power generation side, and NVIDIA's 800V DC architecture white paper proposes facility-level and rack-level two-tier storage schemes.
Intel announced a series of AI innovations at Computex 2026, spanning from chips to system-level solutions. Intel is working with SambaNova and Foxconn to build rack-scale AI inference infrastructure based on Xeon processors and the SambaNova SN-50 RDU.