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Oct 16Fri
Oct 15Thu
  1. Semiconductor Engineering Chips and Packaging31

    Beyond The Specification: What Really Determines PCIe Retimer Reach?

    The actual reach of a PCIe retimer is not set by the spec but by multiple factors including SerDes architecture, controller intelligence, channel quality, and diagnostics. PCI-SIG typically requires about 36 dB insertion loss tolerance, but leading vendors' retimers can tolerate 40 dB or more, enabling longer PCB traces, more connectors, and greater manufacturing variance. As PCIe Gen6 advances, designs beyond compliance testing, interoperability, and observability become key to real-world deployment reliability.

Oct 13Tue
  1. Marvell Optical Interconnect and Official Announcements44

    ADDING and REPLACING Marvell Unveils Second-generation Structera X, Industry-first Six-channel CXL 3.2 Memory Expanders for AI Inference

    Marvell has launched its second-generation Structera X 3406 and 3506 CXL 3.2 memory expanders, built on an industry-first six-channel DDR4/DDR5 design that increases channel count by 50% over the previous generation, supports PCIe Gen 6, and allows a single controller to support up to 9TB DDR4 or 6TB DDR5.

Oct 12Mon
Oct 10Sat
  1. TechCrunch · AI41

    Amazon and others are done keeping data center deals secret. Is it enough to build trust?

    Amazon says it will no longer use NDAs when negotiating data center deals with local governments, following a similar move by Microsoft earlier this year. The secrecy fueled community backlash against AI infrastructure, with hundreds of pause proposals or laws emerging from New York to San Francisco. TechCrunch’s Equity podcast also discusses why personal AI startups treat trust as the real product.

Oct 8Thu
  1. Semiconductor Engineering Chips and Packaging20

    Perspectives On Test: System Level Test For AI & Data Centers

    Ben Mitchel, senior director of Teradyne's Integrated System Test division, explains why system-level test has become critical for mass production of AI and data center equipment. These devices use multi-chiplet designs and draw thousands of watts, requiring testing under real-world conditions. The Titan HP platform delivers the power, thermal management, and throughput such devices demand.

Sep 24Thu
  1. TrendForce Insights Semiconductor Industry Insights43

    Why CSPs Are Turning to QLC SSDs for KV Cache Storage

    TrendForce has observed that some cloud service providers are adding QLC SSDs to SSD PODs, replacing the default TLC SSD plus HDD configuration. In AI inference, the Prefill and Decode stages repeatedly read and write KV Cache, and as context windows and batch sizes grow, KV Cache capacity needs multiply, prompting vendors to move caching from costly, capacity-limited HBM down to cheaper tiers.

Sep 21Mon
  1. Marvell Optical Interconnect and Official Announcements43

    Marvell to Showcase Industry-First 2nm Optical Technology Demos for AI Data Center Infrastructure at ECOC 2026

    Marvell will present industry-first 2nm optical interconnect demonstrations at ECOC 2026 in Malaga, Spain, September 20–24, 2026, including the first 2nm 400G/lane optical PAM4, the first 2nm 800G ZR/ZR+ pluggable modules with MACsec (driven by the Libra 2nm coherent DSP), and the first 2nm 1.6T ZR and coherent-lite O-band demos.

Sep 14Mon
  1. TrendForce Insights Semiconductor Industry Insights31

    Weekly Radar 001: The GPU is Not the Bottleneck

    TrendForce launched Weekly Radar, a free subscription column that tracks supply and lead times for six component categories—GPU, DRAM, NAND, HDD, ABF, and MLCC—each week. The first issue notes the GPU is the only one of the six with lead times at balanced levels, while ABF lead times are 48-56 weeks, far above the balanced 12 weeks.

Sep 9Wed
Sep 2Wed
Sep 1Tue
Aug 18Tue
  1. AMD Chips and Compute27

    Scaling Impact: 2025-26 Corporate Responsibility Report

    AMD released its 2025-26 Corporate Responsibility Report, reviewing progress on 2020-2025 goals and looking ahead to 2030. From 2020 to 2025, renewable electricity rose from 22% to 58%, operational greenhouse gas emissions fell 30%, AI training and high-performance computing node energy efficiency improved 38x, and AMD systems on the Green500 list grew from 11 to 194; new targets include a 20x improvement in rack-scale AI energy efficiency from 2024 to 2030.

Jul 24Fri
  1. TrendForce Insights Semiconductor Industry Insights45

    Breaking the Memory Bottleneck Part 1: How CXL Unlocks the Memory Capacity KV Cache Needs

    In the first half of 2026, the core constraint of AI inference has shifted from compute to memory, as surging KV Cache demands meet limited memory supply and become the main bottleneck. For Llama 3 70B FP16, model weights are about 140GiB, but the KV Cache reaches 160GiB at 64K context and balloons to 320GiB at 128K, about 2.3 times the weight size.

Jul 10Fri
  1. TrendForce Insights Semiconductor Industry Insights41

    From Backup Power to Critical Infrastructure, AIDC Is Rewriting the Energy Storage Playbook

    TrendForce analysis indicates that large-scale AI data center (AIDC) deployments in 2026 are pushing energy storage from an optional add-on to critical infrastructure. North America urgently needs storage to secure 24/7 power given gas generation's 40-50% share and tight supply of large gas turbines; China has made compute-power coordination part of new infrastructure, making 4-8 hour long-duration storage standard for compute hubs. AIDC storage is deployed on both the data center side and the power generation side, and NVIDIA's 800V DC architecture white paper proposes facility-level and rack-level two-tier storage schemes.

Jun 2Tue