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#高速互连

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Oct 15Thu
  1. Semiconductor Engineering Chips and Packaging26

    Building AI Infrastructure For Greater Choice And Flexibility

    AI training and inference have different demands for memory, compute, and interconnect, pushing AI infrastructure toward heterogeneity. UCIe provides die-to-die standardized connectivity, and with chiplet solutions lets compute, I/O, and memory interfaces be flexibly integrated in one package. At the system level, PCIe, CXL, UALink, and Ethernet must be combined with technologies like HBM4E and LPDDR6, using open standards and interoperability validation to leave room for architectural evolution.

  2. Semiconductor Engineering Chips and Packaging31

    Beyond The Specification: What Really Determines PCIe Retimer Reach?

    The actual reach of a PCIe retimer is not set by the spec but by multiple factors including SerDes architecture, controller intelligence, channel quality, and diagnostics. PCI-SIG typically requires about 36 dB insertion loss tolerance, but leading vendors' retimers can tolerate 40 dB or more, enabling longer PCB traces, more connectors, and greater manufacturing variance. As PCIe Gen6 advances, designs beyond compliance testing, interoperability, and observability become key to real-world deployment reliability.

Oct 14Wed
  1. Semiconductor Engineering Chips and Packaging22

    Blog Review: Oct. 14

    This blog review gathers several engineering articles: Synopsys explores how engineers' roles shift toward defining goals and evaluating trade-offs in autonomous workflows; Siemens explains how UALink over UCIe 3.0 enables cross-vendor interoperability through a standardized interface; Cadence covers GDDR7's channel operation, encoding and protection mechanisms; and Arm improves mobile toxicity speech detection using LiteRT, quantization, KleidiAI and SME2, reducing latency and server load.

Oct 13Tue
Oct 12Mon
  1. Semiconductor Engineering Chips and Packaging44

    Startup Funding: Q3 2026

    In Q3 2026, 80 startups raised more than $8.5 billion combined, with two inference companies each raising $1 billion and nearly $7.5 billion going to 22 companies with rounds of $100 million or more. Investor focus centered on interconnect technology, networking chips and photonics, including co-packaged optics, millimeter-wave plastic waveguides, ferroelectric glass modulators and coherent DSPs for AI optics, while some companies explored replacing constrained HBM with ordinary DRAM or on-chip SRAM.

Oct 8Thu
Sep 9Wed