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#AI硬件

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TodayOct 18Sun
Oct 16Fri
  2. Semiconductor Engineering Chips and Packaging41

    Chip Industry Week In Review

    GlobalFoundries will run two new fabs in Malta, New York, with investment of up to $21B; the first fab is expected to begin production in 2029. FormFactor and Teradyne will jointly develop test technologies for HBM and advanced packaging, with Teradyne investing $300M. CXMT plans to launch DDR5 server RDIMMs using 4F² DRAM cells by year-end; its EUV light source prototype has 90% localization but still needs three to five years before mass production.

  4. TechCrunch · AI51

    Amazon devices chief Panos Panay sees a future where AI devices replace the need to use apps

    Panos Panay, Amazon's SVP of Devices & Alexa, said at TechCrunch Disrupt that personal computing is heading toward ambient computing devices where sensors and AI work proactively in the background — the next generation of users won't open an app for everything but will expect devices to understand their needs, though smartphones will remain important.

Oct 15Thu
  4. The Verge · AI73

    Your secrets aren’t safe with this cute robot toy — they’re on Chinese servers ready to be hacked

    A Verge reporter and hacker Sammy Azdoufal tested Energize Lab’s Eiliko companion robot toy and found its service has no protections at all: full conversation transcripts are stored in a searchable database on Chinese servers, and user profiles are automatically generated covering names, ages, occupations, family members, and psychological states.

  6. Semiconductor Engineering Chips and Packaging51

    How Close Are We To Fully Autonomous Chip Design?

    In a SEMICON West interview, Synopsys CEO Sassine Ghazi said the company has deployed more than 40 task agents, and some customers can hand a spec to the Synopsys Autonomous Agent to automatically generate and verify RTL — a process that used to take multiple engineers several months — though fully autonomous chip design remains out of reach today.

  7. Semiconductor Engineering Chips and Packaging52

    Why Open-Weight AI Matters

    Semiconductor Engineering examines how open-weight AI models affect chip architecture, noting the focus is shifting from peak TOPS to memory bandwidth and capacity, sustained throughput, numerical format flexibility, and deployment security.

  9. Semiconductor Engineering Chips and Packaging26

    Building AI Infrastructure For Greater Choice And Flexibility

    AI training and inference have different demands for memory, compute, and interconnect, pushing AI infrastructure toward heterogeneity. UCIe provides die-to-die standardized connectivity, and with chiplet solutions lets compute, I/O, and memory interfaces be flexibly integrated in one package. At the system level, PCIe, CXL, UALink, and Ethernet must be combined with technologies like HBM4E and LPDDR6, using open standards and interoperability validation to leave room for architectural evolution.

  10. Semiconductor Engineering Chips and Packaging31

    Beyond The Specification: What Really Determines PCIe Retimer Reach?

    The actual reach of a PCIe retimer is not set by the spec but by multiple factors including SerDes architecture, controller intelligence, channel quality, and diagnostics. PCI-SIG typically requires about 36 dB insertion loss tolerance, but leading vendors' retimers can tolerate 40 dB or more, enabling longer PCB traces, more connectors, and greater manufacturing variance. As PCIe Gen6 advances, designs beyond compliance testing, interoperability, and observability become key to real-world deployment reliability.

  12. Lam Research Semiconductor Manufacturing Technology36

    Lam and imec Expand Collaboration to Advance Manufacturability of Next-Gen 3D Integration Technologies, Explore Aether Dry Resist Use Cases

    Lam Research and imec are expanding their joint R&D collaboration with two new directions: advancing manufacturing readiness of 3D integration and advanced packaging, and advancing Aether® dry resist applications in imec's high-NA EUV research environment.

  13. The Verge · AI41

    Square’s new kiosk lets you talk to AI for help with your order

    Square launched Square Kiosk, an ordering terminal with a 21.5-inch touchscreen and an "agentic, conversational voice layer" that understands a seller's menu in real time and responds to customers' natural-language orders, questions, and modification or substitution requests. The device supports presence detection to sense arriving guests and contactless payments. It's for Square Plus or Premium subscription merchants, priced at $1,999 plus a $99 monthly software fee per device.

Oct 14Wed
  1. Semiconductor Engineering Chips and Packaging22

    Blog Review: Oct. 14

    This blog review gathers several engineering articles: Synopsys explores how engineers' roles shift toward defining goals and evaluating trade-offs in autonomous workflows; Siemens explains how UALink over UCIe 3.0 enables cross-vendor interoperability through a standardized interface; Cadence covers GDDR7's channel operation, encoding and protection mechanisms; and Arm improves mobile toxicity speech detection using LiteRT, quantization, KleidiAI and SME2, reducing latency and server load.

  3. Semiconductor Engineering Chips and Packaging25

    Accelerating Advanced IC Package Design: A Methodology for Early and Iterative Optimization of Chiplet Integration

    Cadence proposes an IC package design methodology supporting early and iterative optimization of chiplet integration. As packaging technologies like CoWoS-R and CoWoS-L grow more complex due to surging signal counts and HBM integration, traditional design and analysis flows risk schedule overruns.

  4. Semiconductor Engineering Chips and Packaging16

    Simplify Electronic-Photonic Design Workflows: eBook

    Semiconductor Engineering published an eBook on the natural evolution of EDA toward photonic device, circuit and system design methods. Driven by surging bandwidth demand, power and latency constraints, and the rapid adoption of silicon photonics, traditional EDA flows cannot handle photonics' complex physics and deep integration, and engineers need to move to electronic-photonic design automation (EPDA), a new design paradigm for delivering scalable, manufacturable optoelectronic systems.

  6. NVIDIA Blog35

    European Cities Deploy NVIDIA-Powered AI Agents to Run Smarter Urban Operations

    Multiple cities across the EMEA region, along with software partners, are using NVIDIA accelerated computing to build physical AI agents and digital twins for urban planning, predictive maintenance, and public services. France's Côte-d'Or department deployed a sovereign digital twin based on Nemotron and Omniverse across more than 500 public buildings, cutting document retrieval time from weeks to minutes, lowering operating costs by 10%, with a target of 30% at scale.

Oct 13Tue
  4. NVIDIA Blog68

    All Systems Go: Global PC App Ecosystem Ready for NVIDIA RTX Spark

    NVIDIA announced that RTX Spark laptops go on sale October 16, with up to 128GB unified memory and 1 petaflop of AI compute, alongside multiple software updates released with ecosystem partners.

    Why it matters: The official roundup covers the software ecosystem around the RTX Spark launch, with specific updates and timing for local agent, creative, and developer tools.

  5. Latent Space84

    [AINews] Meta Muse Wonder & Wonder Full: MSL’s Claude 5.5-tier Frontier Model

    Meta Superintelligence Labs released its second-generation model family, Muse Wonder (codename Watermelon) and Muse Wonder Full, scoring 52 and 56 respectively on the third-party Artificial Analysis Intelligence Index v4.3, a clear jump from Muse Spark 1.3's 48, just 6 weeks after the previous generation's release.

    Why it matters: The article gathers third-party benchmarks, pricing, and early hands-on feedback for Meta's new model family, letting readers compare where it actually stands against competitors.

  7. Intel Official Announcements47

    Intel Accelerates Open Infrastructure for the Agentic AI Era

    At the OCP Global Summit, Intel detailed its GPU D-series (codenamed Crescent Island), built on the Xe3P architecture with up to 480 GB LPDDR5X memory, 1.5 TB/s memory bandwidth and 1.3 petaflops of FP8 compute at 350 watts; a single card supports 300-billion-parameter models and an 8-card system supports over 1 trillion parameters.

  8. Marvell Optical Interconnect and Official Announcements44

    ADDING and REPLACING Marvell Unveils Second-generation Structera X, Industry-first Six-channel CXL 3.2 Memory Expanders for AI Inference

    Marvell has launched its second-generation Structera X 3406 and 3506 CXL 3.2 memory expanders, built on an industry-first six-channel DDR4/DDR5 design that increases channel count by 50% over the previous generation, supports PCIe Gen 6, and allows a single controller to support up to 9TB DDR4 or 6TB DDR5.

Oct 12Mon
  2. NVIDIA Blog63

    OCP Global Summit: Amid Ecosystem Adoption, NVIDIA Opens Vera Rubin Architecture to Help Scale AI Factories Worldwide

    At the OCP Global Summit, NVIDIA announced it is contributing Vera Rubin rack and compute tray designs to the OCP through its MGX open architecture. The MGX 1.2 spec adds rack-level blind-mate liquid cooling, a 5000A liquid-cooled busbar, and support for rack deployments of up to 250kW.

    Why it matters: The piece collects multiple open specifications such as MGX 1.2 and Open Data Center Specification v0.7, along with accompanying software, giving readers a view into the open foundations of AI factories.

  4. Marvell Optical Interconnect and Official Announcements42

    Marvell Unveils Second-generation Structera X, Industry-first Six-channel CXL 3.2 Memory Expanders for AI Inference

    Marvell released the second-generation Structera X 3406 and 3506 CXL 3.2 memory expanders, the industry's first six-channel CXL memory expansion products, with 50% more channels than the previous generation, supporting up to 9TB of DDR4 or 6TB of DDR5 per controller and delivering up to 256GB/s of host bandwidth over PCIe 6.0 x16.