GlobalFoundries will run two new fabs in Malta, New York, with investment of up to $21B; the first fab is expected to begin production in 2029. FormFactor and Teradyne will jointly develop test technologies for HBM and advanced packaging, with Teradyne investing $300M. CXMT plans to launch DDR5 server RDIMMs using 4F² DRAM cells by year-end; its EUV light source prototype has 90% localization but still needs three to five years before mass production.
At sub-5nm nodes, interconnects have replaced gate delay as the main bottleneck for SoC power, performance, and area (PPA); via resistance rises exponentially as dimensions shrink, worsening electromigration (EM) and IR drop risks.
Anna Goldie and Azalia Mirhoseini introduced their startup Ricursive Intelligence at TechCrunch Disrupt: using AI to automate chip design so each iteration learns and improves subsequent designs.
Lam Research and imec are expanding their joint R&D collaboration with two new directions: advancing manufacturing readiness of 3D integration and advanced packaging, and advancing Aether® dry resist applications in imec's high-NA EUV research environment.
Researchers from Sandia National Laboratories and the Luxembourg Institute of Science and Technology published a paper that spatially resolves GAAFET leakage pathways using charge self-consistent Non-Equilibrium Green Function simulations based on the Contact Block Reduction method.
Semiconductor Engineering spoke with experts from Synopsys, Silvaco, Vinci, Keysight EDA and Siemens EDA at the Design Automation Conference about the thermal management challenges posed by chip stacking.
Researchers from Columbia University, Google DeepMind, and Google have published a paper proposing Back-to-the-Future (BTTF), an end-to-end agentic framework that automates post-simulation waveform debugging in chip verification.
Semiconductor Engineering collects multiple recent chip technology papers, covering spatially deterministic nucleation of 2D semiconductors from KAIST and other institutions, the Hyper-NA EUV lithography system with a numerical aperture of at least 0.75 from Zeiss SMT and ASML, and BARE-AI from the University of Florida and others, which uses built-in performance monitors to defend against bit-flip attacks in AI hardware.
Researchers from UIUC, NETL, Argonne National Laboratory and Monash University published a paper in Nature Communications using monolayer-assembled carbon dots to form an atomically thin van der Waals interface layer, enabling ultrathin high-κ oxides to be deposited on 2D semiconductors.
Researchers from KAIST, TDS Innovation, Hanyang University, UNIST and other institutions published a paper in Nature proposing an etching-flux-mediated single-nucleus nucleation method for 2D semiconductors that deterministically positions a single nucleation event at a designated location. Conventional strategies can only control nucleation density and achieve area-selective growth, but cannot determine where an individual nucleus lands within the growth area. Published in October 2026, the paper is open access.
Microsoft unveiled its third-generation in-house AI chip Maia 300, positioned as the "primary AI inference system" for its products and services, with production planned from 2027 and the Azure Maia family scaling to multi-gigawatt deployments starting in 2027.
In Q3 2026, 80 startups raised more than $8.5 billion combined, with two inference companies each raising $1 billion and nearly $7.5 billion going to 22 companies with rounds of $100 million or more. Investor focus centered on interconnect technology, networking chips and photonics, including co-packaged optics, millimeter-wave plastic waveguides, ferroelectric glass modulators and coherent DSPs for AI optics, while some companies explored replacing constrained HBM with ordinary DRAM or on-chip SRAM.
Ben Mitchel, senior director of Teradyne's Integrated System Test division, explains why system-level test has become critical for mass production of AI and data center equipment. These devices use multi-chiplet designs and draw thousands of watts, requiring testing under real-world conditions. The Titan HP platform delivers the power, thermal management, and throughput such devices demand.
Semiconductor fabs are using real-time equipment sensor data and AI/ML inference models to move yield anomaly detection inside process modules, accelerating yield learning and improving advanced process control (APC). Equipment sensor sampling has risen from about once per second to once every few tens of milliseconds, data types have grown at least 10x compared with a decade ago, and some fabs generate hundreds of petabytes per year. How to process data in sub-second timescales while preserving context and connectivity is the main data management challenge shift left brings.
Every test, inspection and monitoring method for advanced chips has physical, spatial or temporal blind spots, and no single technology provides a complete picture. Vendors including Nordson, ZEISS and Teradyne note that defects such as solder voids and head-in-pillow can pass electrical test yet cause early failures, while X-ray still faces trade-offs among precision, throughput and resolution for stacked dies and TSV inspection.
In advanced packaging, defects accumulate value step by step through the process flow, and shrinking feature sizes push inspection requirements toward front-end levels, spanning surface particles, sidewall cracks, buried defects, microbump anomalies and bonding voids. Manufacturers need to combine complementary methods—high-sensitivity 2D inspection, infrared subsurface inspection and 3D metrology—in a unified workflow, balancing sensitivity with throughput, and use effective classification to turn inspection results into actionable process information.
Researchers from HUST, Hong Kong Polytechnic University, UCSB, and the National University of Singapore published a Nature Communications paper demonstrating high-performance ballistic-transport WSe2 monolayer p-type transistors via oxygen p-type doping. The approach solves insufficient doping and high contact resistance caused by MIGS from metal deposition, boosting p-type on-current, aiming to let 2D semiconductors surpass silicon at sub-1nm nodes for CMOS circuits.
A UC Santa Cruz team released the first design space exploration of backside clock meshes, implemented on OpenROAD and GT2N using a 2nm GAAFET BSPDN process. Backside power delivery provides thick, low-resistance metal layers on the wafer's backside, reducing clock skew and power; since flip-flops stay on the frontside, all connections run through silicon vias. The paper was released on arXiv in October 2026 (arXiv:2610.02401).
imec is advancing its CFET device roadmap, projecting that the industry may shift to CFET architectures from the A7 logic node, shrinking standard cells to 4.5-track and below.
Semiconductor Engineering rounds up this week's blogs: a Siemens team explores how CFETs and buried power rails can shrink chip area and improve energy efficiency to meet the needs of AI accelerators, data centers, and mobile processors; Synopsys and Cadence analyze the collaborative advantages of agentic AI in EDA; Arm introduces the AMBA C2C extension for chiplet connectivity.
Precisely aligning and fixing fiber array units—FAU coupling—has become a critical bottleneck in CPO manufacturing and testing. At SEMICON Taiwan 2026, TSMC unveiled an upgraded COUPE roadmap: per-chip bandwidth reaching 3.2 Tbps in 2026, doubling to 6.4 Tbps in 2027, with a long-term target exceeding 51.2 Tbps. Integrating optics on the substrate can deliver a 4X power-efficiency gain, with OOI reaching 10X.
Using SEMulator3D digital twin modeling, Lam Research validated a self-aligned complementary field-effect transistor (SA-CFET) architecture that could extend CMOS scaling beyond the 10-angstrom node.
Lam Research has opened its largest US warehouse in Livermore, California—a 470,000-square-foot logistics and supply chain hub built to support semiconductor supply chain pressures driven by AI technology demand. A 40,000-square-foot automated storage and retrieval system with 15 robots cuts parts retrieval time from 6 minutes to under 30 seconds, 12 times faster than the existing system. The center is expected to support more than 200 jobs by 2027.
NAND suppliers are shifting capacity toward enterprise SSDs on recovering demand, but eSSD lead times still stretch to 16 weeks, far above the 8 weeks of a balanced market, and overall supply remains insufficient. Other highlights this week include reports that SK hynix is in early talks with Intel about producing memory chips in the US, and Huawei moving its Ascend 960DT up three quarters to early 2027 to catch up with NVIDIA.
AI's demand for larger, more complex chip packaging is pushing the industry to explore panel-level packaging (PLP): replacing round wafers with rectangular panels to improve area utilization and scalability beyond traditional wafer-level packaging size limits. Lam Research is advancing the technology toward production readiness through tool innovation and infrastructure investments, including the Salzburg Panel Center of Excellence. The technology still faces challenges in uniformity control, yield management, and industry standards.
At the SPIE Photomask and EUV Lithography conference, Intel Foundry and ASML reported progress on High NA EUV volume readiness; the technology has already been used in production of some Core Ultra Series 3 (Panther Lake) processors on Intel's 18A process.
Lam Research used SEMulator3D® integrated stress modeling to predict stress non-uniformity across GAA stacked nanosheet channels before fabrication — nFET stress differences reach 400–800 MPa, while pFET stays below 200 MPa. DOE experiments show that channel thickness, fin width, and lateral etch jointly affect stress uniformity, with increasing the topmost channel thickness from 4 nm to 7 nm significantly reducing the stress difference.
At the 2026 VLSI Symposium, Intel Foundry announced that Intel 18A-P has entered risk production, delivering 9% higher performance at the same power or 18% lower power at the same performance compared with Intel 18A, and is fully design-rule compatible with Intel 18A to reuse existing IP.