GlobalFoundries will run two new fabs in Malta, New York, with investment of up to $21B; the first fab is expected to begin production in 2029. FormFactor and Teradyne will jointly develop test technologies for HBM and advanced packaging, with Teradyne investing $300M. CXMT plans to launch DDR5 server RDIMMs using 4F² DRAM cells by year-end; its EUV light source prototype has 90% localization but still needs three to five years before mass production.
AI training and inference have different demands for memory, compute, and interconnect, pushing AI infrastructure toward heterogeneity. UCIe provides die-to-die standardized connectivity, and with chiplet solutions lets compute, I/O, and memory interfaces be flexibly integrated in one package. At the system level, PCIe, CXL, UALink, and Ethernet must be combined with technologies like HBM4E and LPDDR6, using open standards and interoperability validation to leave room for architectural evolution.
Researchers from ETH Zurich and NYU published a paper presenting the first comprehensive experimental characterization of power consumption on real HBM2 DRAM chips, with 13 new findings and 6 key conclusions. Read operations draw significantly more current than other operations, and flipping all bank group bus signals increases power by 29.4% over holding them constant. Based on this, the team constructed access patterns that on average consume 23.6% more power than the JEDEC-specified maximum power measurement loop across 36 tested HBM2 chips.
Cadence proposes an IC package design methodology supporting early and iterative optimization of chiplet integration. As packaging technologies like CoWoS-R and CoWoS-L grow more complex due to surging signal counts and HBM integration, traditional design and analysis flows risk schedule overruns.
Memory supply tightness will persist through 2027, with DRAM lead times at 20 weeks versus a balanced level of 8 weeks; vendors are shifting PC DRAM capacity to server DRAM, and HDD lead times remain at 50 weeks.
TrendForce's weekly report shows DRAM lead times have reached 20 weeks (versus a balanced level of 8 weeks), and the shortage is limiting the ability of some NAND vendors to support enterprise SSD solutions.
Through a decade of venture investing, SK hynix has evolved its corporate VC model from "tech sensing" to "path finding," turning internal R&D, mass production and customer resources into assets startups can leverage.
NAND suppliers are shifting capacity toward enterprise SSDs on recovering demand, but eSSD lead times still stretch to 16 weeks, far above the 8 weeks of a balanced market, and overall supply remains insufficient. Other highlights this week include reports that SK hynix is in early talks with Intel about producing memory chips in the US, and Huawei moving its Ascend 960DT up three quarters to early 2027 to catch up with NVIDIA.
TrendForce says 4hi HBM samples will enter supplier views in early 3Q26, with NVIDIA and other AI chip vendors evaluating low-stack configurations to cope with the HBM shortage. The spec has real use cases in edge AI scenarios like autonomous driving and robotics; SK hynix previously supplied HBM2E to Waymo in 2024 with automotive certification, but near-term demand contribution remains very low.
SK hynix, together with researchers from UVA, UIUC, NTU, MIT and Yonsei University, has published a co-packaged optics (CPO) technology roadmap in Nature Electronics. The corresponding authors are Seunghoon Hong, SK hynix AI Infra Team Lead, and UVA professor Kyusang Lee.
As test-time scaling rises, the AI industry's focus is shifting from training to inference, bringing structural changes to the memory hierarchy. In the first half of 2026, NVIDIA and Google respectively launched CMX, Rubin integrated Groq LPX, and the TPU v8i designed for inference (with 72 GB more HBM3e and 384 MB SRAM than the TPU v8t).