GlobalFoundries will run two new fabs in Malta, New York, with investment of up to $21B; the first fab is expected to begin production in 2029. FormFactor and Teradyne will jointly develop test technologies for HBM and advanced packaging, with Teradyne investing $300M. CXMT plans to launch DDR5 server RDIMMs using 4F² DRAM cells by year-end; its EUV light source prototype has 90% localization but still needs three to five years before mass production.
The AMBA ecosystem is developing a new specification, AMBA C2C, which builds on AMBA CHI C2C to provide a unified, scalable chiplet interconnect foundation covering both AXI and CHI protocols.
AI training and inference have different demands for memory, compute, and interconnect, pushing AI infrastructure toward heterogeneity. UCIe provides die-to-die standardized connectivity, and with chiplet solutions lets compute, I/O, and memory interfaces be flexibly integrated in one package. At the system level, PCIe, CXL, UALink, and Ethernet must be combined with technologies like HBM4E and LPDDR6, using open standards and interoperability validation to leave room for architectural evolution.
Semiconductor Engineering spoke with experts from Synopsys, Silvaco, Vinci, Keysight EDA and Siemens EDA at the Design Automation Conference about the thermal management challenges posed by chip stacking.
Cadence proposes an IC package design methodology supporting early and iterative optimization of chiplet integration. As packaging technologies like CoWoS-R and CoWoS-L grow more complex due to surging signal counts and HBM integration, traditional design and analysis flows risk schedule overruns.
TSMC and GlobalFoundries signed a $2 billion agreement under which GlobalFoundries will manufacture silicon interposers for TSMC's CoWoS advanced packaging ecosystem at its Malta, New York plant, with volume production ramping in the first half of 2028.
Ben Mitchel, senior director of Teradyne's Integrated System Test division, explains why system-level test has become critical for mass production of AI and data center equipment. These devices use multi-chiplet designs and draw thousands of watts, requiring testing under real-world conditions. The Titan HP platform delivers the power, thermal management, and throughput such devices demand.
Semiconductor process control is shifting from visual inspection to electrical measurement. In advanced packaging, residual charge and static accumulation are hard to detect with conventional inspection and metrology, yet they affect yield, device reliability and manufacturing consistency; the problem grows worse with hygroscopic films, dielectric layers and plasma processes. Onto Innovation offers full-wafer mapping and panel-level high-resolution mapping to locate local non-uniformities and hotspots.
As heterogeneous integration evolves from 2.5D interposers and CoWoS to hybrid bonding and 3D stacking, the yield sensitivity and defect mechanisms of advanced packaging differ sharply from front-end logic and standard packaging, and the industry has long lacked dedicated metrology, characterization and analysis frameworks. The article presents an integrated methodology to accelerate advanced packaging process development and sustain production control.
Advantest's Dong Ong talks with ISIG co-founder and CEO Salah Nasri about competitive advantage in the semiconductor industry over the next decade. In the AI era, industry value is shifting from transistor process nodes and single chips to advanced packaging, system integration, software and platform ecosystems; performance depends on how efficiently an entire system moves data, manages energy and coordinates compute, and future winners will be vendors that combine technology, platforms and partnerships into a value system.
Every test, inspection and monitoring method for advanced chips has physical, spatial or temporal blind spots, and no single technology provides a complete picture. Vendors including Nordson, ZEISS and Teradyne note that defects such as solder voids and head-in-pillow can pass electrical test yet cause early failures, while X-ray still faces trade-offs among precision, throughput and resolution for stacked dies and TSV inspection.
In advanced packaging, defects accumulate value step by step through the process flow, and shrinking feature sizes push inspection requirements toward front-end levels, spanning surface particles, sidewall cracks, buried defects, microbump anomalies and bonding voids. Manufacturers need to combine complementary methods—high-sensitivity 2D inspection, infrared subsurface inspection and 3D metrology—in a unified workflow, balancing sensitivity with throughput, and use effective classification to turn inspection results into actionable process information.
imec is advancing its CFET device roadmap, projecting that the industry may shift to CFET architectures from the A7 logic node, shrinking standard cells to 4.5-track and below.
TrendForce's weekly radar focuses on server CPUs: agentic AI has pushed lead times to 25–30 weeks, well above the balanced level of 16–20 weeks. Meta's AI agent Muse reportedly surpassed ChatGPT in downloads early after launch, driving AMD's market cap past $1 trillion for the first time, and at Connect 2026 Meta unveiled the Meta Charm handheld device powered by Muse.
TrendForce takes a deep dive into 3D advanced packaging and hybrid bonding: TSMC's SoIC uses 3D interconnect with 56x the interconnect density and 5x the energy efficiency of CoWoS, entered mass production in 2025 with a 6µm bond pitch, and plans to shrink to 4.5µm by 2029; Intel's Foveros Direct, at a 9µm pitch, enters mass production in 1H26 with the Clearwater Forest Xeon 6+.
AI's demand for larger, more complex chip packaging is pushing the industry to explore panel-level packaging (PLP): replacing round wafers with rectangular panels to improve area utilization and scalability beyond traditional wafer-level packaging size limits. Lam Research is advancing the technology toward production readiness through tool innovation and infrastructure investments, including the Salzburg Panel Center of Excellence. The technology still faces challenges in uniformity control, yield management, and industry standards.
AMD announced it will be first to offer native UCIe 1.1 interface support in Versal adaptive SoCs, enabling low-power, high-bandwidth communication between adaptive SoCs and co-packaged specialty chiplets.
TrendForce maps the latest landscape of 2.5D/3D advanced packaging in the AI chip supply chain: TSMC's 5.5x reticle CoWoS is in mass production with yields above 98%, with plans to expand beyond 14x after 2029; Intel's EMIB-T yields have improved significantly, expanding beyond 8x this year and over 12x by 2028, targeting customer mass production in 2027.
Intel has appointed Seok-Hee Lee as executive vice president of Intel Foundry, reporting directly to CEO Lip-Bu Tan and overseeing advanced packaging, system integration, back-end technology development, and back-end manufacturing.