Semiconductor Engineering spoke with experts from Synopsys, Silvaco, Vinci, Keysight EDA and Siemens EDA at the Design Automation Conference about the thermal management challenges posed by chip stacking.
Cadence proposes an IC package design methodology supporting early and iterative optimization of chiplet integration. As packaging technologies like CoWoS-R and CoWoS-L grow more complex due to surging signal counts and HBM integration, traditional design and analysis flows risk schedule overruns.
TSMC and GlobalFoundries signed a $2 billion agreement under which GlobalFoundries will manufacture silicon interposers for TSMC's CoWoS advanced packaging ecosystem at its Malta, New York plant, with volume production ramping in the first half of 2028.
As heterogeneous integration evolves from 2.5D interposers and CoWoS to hybrid bonding and 3D stacking, the yield sensitivity and defect mechanisms of advanced packaging differ sharply from front-end logic and standard packaging, and the industry has long lacked dedicated metrology, characterization and analysis frameworks. The article presents an integrated methodology to accelerate advanced packaging process development and sustain production control.
TrendForce takes a deep dive into 3D advanced packaging and hybrid bonding: TSMC's SoIC uses 3D interconnect with 56x the interconnect density and 5x the energy efficiency of CoWoS, entered mass production in 2025 with a 6µm bond pitch, and plans to shrink to 4.5µm by 2029; Intel's Foveros Direct, at a 9µm pitch, enters mass production in 1H26 with the Clearwater Forest Xeon 6+.
TrendForce maps the latest landscape of 2.5D/3D advanced packaging in the AI chip supply chain: TSMC's 5.5x reticle CoWoS is in mass production with yields above 98%, with plans to expand beyond 14x after 2029; Intel's EMIB-T yields have improved significantly, expanding beyond 8x this year and over 12x by 2028, targeting customer mass production in 2027.