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The Verge · AIAI score6262 A week with RTX Spark: everything we’ve learned using Nvidia’s new laptops
Three editors at The Verge spent a week trying five laptops with Nvidia's RTX Spark N1X chip, including the Surface Laptop Ultra, Asus ProArt P16, Lenovo Yoga 9n and HP OmniBook Ultra, priced from $2,599.99 to $6,999.99.
Semiconductor Engineering Chips and PackagingAI score4141 Chip Industry Week In Review
GlobalFoundries will run two new fabs in Malta, New York, with investment of up to $21B; the first fab is expected to begin production in 2029. FormFactor and Teradyne will jointly develop test technologies for HBM and advanced packaging, with Teradyne investing $300M. CXMT plans to launch DDR5 server RDIMMs using 4F² DRAM cells by year-end; its EUV light source prototype has 90% localization but still needs three to five years before mass production.
SK hynix Memory TechnologyAI score4545 “Memory-Centric Server Systems Are the Future”: SK hynix Presents Its Next-Generation AI Infrastructure Vision at OCP Global Summit 2026
SK hynix presented several next-generation memory solutions for AI servers at OCP Global Summit 2026, held October 12–15 in San Jose.
NVIDIA BlogAI score5757 Be There for the Beginning: Celebrate the Launch of NVIDIA RTX Spark
NVIDIA announced that RTX Spark officially launches tomorrow, positioned as a Windows PC with local AI support aimed at creators, gamers and AI agents.
The Verge · AIAI score5858 How Windows is being optimized for Nvidia’s RTX Spark laptops
The Verge's hands-on with the first RTX Spark laptops details the adaptation work Microsoft and Nvidia have done in Windows. An Arm CPU plus Blackwell GPU and unified memory can run large models locally, and Windows offers a Get Started two-step agent installation experience with launch support for Hermes, Perplexity, and OpenClaw.
The Verge · AIAI score5353 Amazon’s always-listening Bee wearable can now help you buy stuff
Amazon has launched two always-listening AI devices, the Bee Frontier ($74.99, on sale today) and the Bee Eclipse ($99.99, coming soon), which can summarize conversations, generate to-dos, and integrate with services like Gmail, Google Calendar, Outlook, and Apple HealthKit.
Semiconductor Engineering Chips and PackagingAI score5555 Thermal Co-Simulation Testing Of Co-Packaged Optics
Ayar Labs and GUC jointly ran thermal co-simulations on a CoWoS-L package integrating 8 TeraPHY optical engines, 2 XPUs, and 8 HBM4 modules; the package draws over 3kW of power and provides a full-duplex optical interface of more than 100 Tbps.
Semiconductor Engineering Chips and PackagingAI score4040 AMBA C2C: Moving Forward With A Converged AMBA Foundation For C2C Connectivity
The AMBA ecosystem is developing a new specification, AMBA C2C, which builds on AMBA CHI C2C to provide a unified, scalable chiplet interconnect foundation covering both AXI and CHI protocols.
Semiconductor Engineering Chips and PackagingAI score2626 Building AI Infrastructure For Greater Choice And Flexibility
AI training and inference have different demands for memory, compute, and interconnect, pushing AI infrastructure toward heterogeneity. UCIe provides die-to-die standardized connectivity, and with chiplet solutions lets compute, I/O, and memory interfaces be flexibly integrated in one package. At the system level, PCIe, CXL, UALink, and Ethernet must be combined with technologies like HBM4E and LPDDR6, using open standards and interoperability validation to leave room for architectural evolution.
Semiconductor Engineering Chips and PackagingAI score3131 Beyond The Specification: What Really Determines PCIe Retimer Reach?
The actual reach of a PCIe retimer is not set by the spec but by multiple factors including SerDes architecture, controller intelligence, channel quality, and diagnostics. PCI-SIG typically requires about 36 dB insertion loss tolerance, but leading vendors' retimers can tolerate 40 dB or more, enabling longer PCB traces, more connectors, and greater manufacturing variance. As PCIe Gen6 advances, designs beyond compliance testing, interoperability, and observability become key to real-world deployment reliability.
TrendForce Insights Semiconductor Industry InsightsAI score5555 The Inference Era Is Also a CPU Story
At OCP Global Summit 2026, AMD CEO Lisa Su called this the year of inference, estimating inference accounts for about 60% of the market, and raised CPU TAM forecasts three times due to agent workloads, expecting the market to exceed $200 billion by 2030.
Lam Research Semiconductor Manufacturing TechnologyAI score3636 Lam and imec Expand Collaboration to Advance Manufacturability of Next-Gen 3D Integration Technologies, Explore Aether Dry Resist Use Cases
Lam Research and imec are expanding their joint R&D collaboration with two new directions: advancing manufacturing readiness of 3D integration and advanced packaging, and advancing Aether® dry resist applications in imec's high-NA EUV research environment.
Semiconductor Engineering Chips and PackagingAI score3838 Why Heat Is Becoming A Bigger Chip Design Issue
Semiconductor Engineering spoke with experts from Synopsys, Silvaco, Vinci, Keysight EDA and Siemens EDA at the Design Automation Conference about the thermal management challenges posed by chip stacking.
Semiconductor Engineering Chips and PackagingAI score2525 Accelerating Advanced IC Package Design: A Methodology for Early and Iterative Optimization of Chiplet Integration
Cadence proposes an IC package design methodology supporting early and iterative optimization of chiplet integration. As packaging technologies like CoWoS-R and CoWoS-L grow more complex due to surging signal counts and HBM integration, traditional design and analysis flows risk schedule overruns.
Semiconductor Engineering Chips and PackagingAI score1616 Simplify Electronic-Photonic Design Workflows: eBook
Semiconductor Engineering published an eBook on the natural evolution of EDA toward photonic device, circuit and system design methods. Driven by surging bandwidth demand, power and latency constraints, and the rapid adoption of silicon photonics, traditional EDA flows cannot handle photonics' complex physics and deep integration, and engineers need to move to electronic-photonic design automation (EPDA), a new design paradigm for delivering scalable, manufacturable optoelectronic systems.
Semiconductor Engineering Chips and PackagingAI score3333 Generative AI On A General-Purpose Neural Processor (GPNPU)
Quadric proposed the General-Purpose Neural Processor (GPNPU) in an IEEE paper, a single programmable processor architecture delivered as configurable IP that unifies scalar, vector and matrix execution into one ISA and a C++/Python programming model.
SK hynix Memory TechnologyAI score4343 [Inside the Research] In the AI era, NAND moves beyond storage to computing… 3D FeNAND co-optimization at IEEE
An SK hynix research team published a paper at the 2025 IEEE International Electron Devices Meeting (IEDM) proposing co-optimization of cell, non-cell, and page schemes to improve the energy efficiency of analog compute-in-memory (A-CiM) based on 3D FeNAND.
AMD Chips and ComputeAI score1212 OCP 2026 Keynote Replay: Building the Next Era of AI Infrastructure
AMD released the replay of its OCP 2026 keynote themed "Building the Next Era of AI Infrastructure." Downloads on the page require first accepting AMD's trademark usage terms, and the AMD trademarks may only be used to promote products containing AMD processors.
The Verge · AIAI score5353 DLSS 5 gets toned down for its Hogwarts Legacy debut next month
NVIDIA's DLSS 5 officially arrives in Hogwarts Legacy on November 5; new comparison screenshots show facial and environmental changes are noticeably more restrained than in the early-year demos, to a degree similar to NBA 2K27.
The Verge · AIAI score5959 Apple launches HomeView, its first smart display for the home
Apple has launched its first smart home display, HomeView, priced at $299. Pre-orders are open now, with shipping on November 13 and an initial launch across eight countries including the US, UK, and Canada.
Marvell Optical Interconnect and Official AnnouncementsAI score4444 Marvell Bolsters Connectivity Portfolio with New 3.2T Protocol-aware Retimer and Second-generation 1.6T AEC DSP
Marvell released two interconnect chips for AI scale-up infrastructure: the Alaska E 3.2T protocol-aware retimer delivers 3.2 Tbps of bandwidth through 16 lanes of 224G PAM4.
Intel Official AnnouncementsAI score4747 Intel Accelerates Open Infrastructure for the Agentic AI Era
At the OCP Global Summit, Intel detailed its GPU D-series (codenamed Crescent Island), built on the Xe3P architecture with up to 480 GB LPDDR5X memory, 1.5 TB/s memory bandwidth and 1.3 petaflops of FP8 compute at 350 watts; a single card supports 300-billion-parameter models and an 8-card system supports over 1 trillion parameters.
Marvell Optical Interconnect and Official AnnouncementsAI score4444 ADDING and REPLACING Marvell Unveils Second-generation Structera X, Industry-first Six-channel CXL 3.2 Memory Expanders for AI Inference
Marvell has launched its second-generation Structera X 3406 and 3506 CXL 3.2 memory expanders, built on an industry-first six-channel DDR4/DDR5 design that increases channel count by 50% over the previous generation, supports PCIe Gen 6, and allows a single controller to support up to 9TB DDR4 or 6TB DDR5.
The DecoderAI score5454 Microsoft plans to scale its own Maia AI chips to gigawatt levels by 2027
Microsoft announced it will deploy its Azure Maia AI chips at multi-gigawatt scale starting in 2027, with executive Scott Guthrie saying they will become the primary inference system for Microsoft's products.
NVIDIA BlogSelectedAI score6363 OCP Global Summit: Amid Ecosystem Adoption, NVIDIA Opens Vera Rubin Architecture to Help Scale AI Factories Worldwide
At the OCP Global Summit, NVIDIA announced it is contributing Vera Rubin rack and compute tray designs to the OCP through its MGX open architecture. The MGX 1.2 spec adds rack-level blind-mate liquid cooling, a 5000A liquid-cooled busbar, and support for rack deployments of up to 250kW.
Why it matters: The piece collects multiple open specifications such as MGX 1.2 and Open Data Center Specification v0.7, along with accompanying software, giving readers a view into the open foundations of AI factories.
AMD Official AnnouncementsAI score4646 Introducing AMD Helion, Agentic AI Compute at Rack Scale
AMD launched the Helion agentic AI rack-scale solution, an open blueprint for agentic AI infrastructure designed based on OCP specifications.
Marvell Optical Interconnect and Official AnnouncementsAI score4242 Marvell Unveils Second-generation Structera X, Industry-first Six-channel CXL 3.2 Memory Expanders for AI Inference
Marvell released the second-generation Structera X 3406 and 3506 CXL 3.2 memory expanders, the industry's first six-channel CXL memory expansion products, with 50% more channels than the previous generation, supporting up to 9TB of DDR4 or 6TB of DDR5 per controller and delivering up to 256GB/s of host bandwidth over PCIe 6.0 x16.
The Verge · AIAI score5555 Microsoft’s new AI chip makes it less reliant on Nvidia’s GPUs
Microsoft unveiled its third-generation in-house AI chip Maia 300, positioned as the "primary AI inference system" for its products and services, with production planned from 2027 and the Azure Maia family scaling to multi-gigawatt deployments starting in 2027.
AMD Chips and ComputeAI score4646 Introducing AMD Helion, Agentic AI Compute at Rack Scale
AMD has launched the AMD Helion agentic AI rack, an open blueprint for agentic AI infrastructure designed to Open Compute Project specifications and powered by AMD compute.
TrendForce Insights Semiconductor Industry InsightsAI score4646 Weekly Radar 005: AI Demand Pulls DRAM Supply Toward Servers
Memory supply tightness will persist through 2027, with DRAM lead times at 20 weeks versus a balanced level of 8 weeks; vendors are shifting PC DRAM capacity to server DRAM, and HDD lead times remain at 50 weeks.
Semiconductor Engineering Chips and PackagingAI score4444 Startup Funding: Q3 2026
In Q3 2026, 80 startups raised more than $8.5 billion combined, with two inference companies each raising $1 billion and nearly $7.5 billion going to 22 companies with rounds of $100 million or more. Investor focus centered on interconnect technology, networking chips and photonics, including co-packaged optics, millimeter-wave plastic waveguides, ferroelectric glass modulators and coherent DSPs for AI optics, while some companies explored replacing constrained HBM with ordinary DRAM or on-chip SRAM.
Arista Switches and Official AnnouncementsAI score5656 Arista Announces Rack-Scale Architectures for Scale-Up and Scale-Out AI Fabrics
Arista Networks (NYSE: ANET) announced an open Ethernet rack-scale portfolio on October 7, 2026, in collaboration with AMD, Arm, Broadcom, d-Matrix, Meta, Microsoft, Qualcomm and others, extending Ethernet into the scale-up domain based on its ESUN initiative.
TechCrunch · AIAI score4141 Natura’s $99 smart ring puts AI agents on your finger
AI hardware startup Natura has launched Interface, a $99 smart ring that summons AI agents to complete tasks with a press of the finger, while also supporting health tracking such as heart rate, HRV, and sleep.
Marvell Optical Interconnect and Official AnnouncementsAI score2424 Marvell to Showcase Open AI Infrastructure Solutions at OCP Global Summit 2026
Marvell will showcase its portfolio of AI data center infrastructure solutions—spanning switching, interconnect, memory, and storage—at OCP Global Summit 2026 in San Jose, October 12–15, at booth #B31.
Ars Technica · AIAI score3838 Nvidia's big bet on physical AI aims for safer robotaxis, humanoid robots
Nvidia's Halos operating system targets physical AI, continuously monitoring every hardware module and software library to quickly detect failures and isolating safety-critical compute workloads. The suite also includes the Holoscan Sensor Bridge, virtual environment simulation testing, and a safety inspection lab program, and has expanded from autonomous driving to robotics. Because safety definitions differ vastly between a robot vacuum and a warehouse forklift, Halos offers a programmable interface so developers can customize safety features without breaking the underlying infrastructure.
Semiconductor Engineering Chips and PackagingAI score2020 Perspectives On Test: System Level Test For AI & Data Centers
Ben Mitchel, senior director of Teradyne's Integrated System Test division, explains why system-level test has become critical for mass production of AI and data center equipment. These devices use multi-chiplet designs and draw thousands of watts, requiring testing under real-world conditions. The Titan HP platform delivers the power, thermal management, and throughput such devices demand.
Semiconductor Engineering Chips and PackagingAI score5656 CPO Testing Faces A Moving Target Problem
Semiconductor Engineering gathered experts from Teradyne, Advantest, ISE Labs and Keysight to discuss CPO/NPO test challenges.
Semiconductor Engineering Chips and PackagingAI score2121 The FAaST Track: Enabling Advanced Packaging Through Electrical Process Control
Semiconductor process control is shifting from visual inspection to electrical measurement. In advanced packaging, residual charge and static accumulation are hard to detect with conventional inspection and metrology, yet they affect yield, device reliability and manufacturing consistency; the problem grows worse with hygroscopic films, dielectric layers and plasma processes. Onto Innovation offers full-wafer mapping and panel-level high-resolution mapping to locate local non-uniformities and hotspots.
Semiconductor Engineering Chips and PackagingAI score2121 From Process Learning To Production Control: Trends In Advanced Packaging And Implications To Characterization And Test
As heterogeneous integration evolves from 2.5D interposers and CoWoS to hybrid bonding and 3D stacking, the yield sensitivity and defect mechanisms of advanced packaging differ sharply from front-end logic and standard packaging, and the industry has long lacked dedicated metrology, characterization and analysis frameworks. The article presents an integrated methodology to accelerate advanced packaging process development and sustain production control.