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#硅光

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Oct 14Wed
  1. Semiconductor Engineering Chips and Packaging16

    Simplify Electronic-Photonic Design Workflows: eBook

    Semiconductor Engineering published an eBook on the natural evolution of EDA toward photonic device, circuit and system design methods. Driven by surging bandwidth demand, power and latency constraints, and the rapid adoption of silicon photonics, traditional EDA flows cannot handle photonics' complex physics and deep integration, and engineers need to move to electronic-photonic design automation (EPDA), a new design paradigm for delivering scalable, manufacturable optoelectronic systems.

Oct 7Wed
  1. Semiconductor Engineering Chips and Packaging35

    Ultra-Compact Photonic Bends Reduce Loss While Meeting Foundry Rules (Georgia Tech)

    Georgia Tech researchers published an ultra-compact integrated photonic waveguide bend design method in Optics Letters, achieving low loss at an extremely small radius of 2.3 µm. The method introduces new contour constraints in a topology optimization framework, reducing sensitivity to manufacturing process variations while satisfying commercial foundry design rule checks, and has been experimentally validated.

Sep 21Mon
  1. Marvell Optical Interconnect and Official Announcements43

    Marvell to Showcase Industry-First 2nm Optical Technology Demos for AI Data Center Infrastructure at ECOC 2026

    Marvell will present industry-first 2nm optical interconnect demonstrations at ECOC 2026 in Malaga, Spain, September 20–24, 2026, including the first 2nm 400G/lane optical PAM4, the first 2nm 800G ZR/ZR+ pluggable modules with MACsec (driven by the Libra 2nm coherent DSP), and the first 2nm 1.6T ZR and coherent-lite O-band demos.

Sep 10Thu
  1. TrendForce Insights Semiconductor Industry Insights42

    Why Everyone Is Talking About Hybrid Bonding, and Who Is in the Race

    TrendForce takes a deep dive into 3D advanced packaging and hybrid bonding: TSMC's SoIC uses 3D interconnect with 56x the interconnect density and 5x the energy efficiency of CoWoS, entered mass production in 2025 with a 6µm bond pitch, and plans to shrink to 4.5µm by 2029; Intel's Foveros Direct, at a 9µm pitch, enters mass production in 1H26 with the Clearwater Forest Xeon 6+.

Sep 9Wed
Aug 4Tue