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AMD Chips and Compute·· 2026-08-25AI score38

AMD to Bring UCIe Connectivity to Select AMD Versal Adaptive SoCs

AMD to Bring UCIe Connectivity to Select AMD Versal Adaptive SoCs

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AMD announced it will be first to offer native UCIe 1.1 interface support in Versal adaptive SoCs, enabling low-power, high-bandwidth communication between adaptive SoCs and co-packaged specialty chiplets.

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AMD will offer the first Versal adaptive SoCs supporting Universal Chiplet Interconnect Express connectivity, enabling direct communication with co-packaged chiplets built for specialized workloads.

Published August 25, 2026

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What’s the News? AMD will offer the first Versal™ adaptive SoCs with native support for Universal Chiplet Interconnect Express (UCIe®) 1.1 interfaces,1 enabling low-power, high-bandwidth communication between co-packaged AMD adaptive SoCs and specialized chiplets.

Why It Matters? As designers seek greater flexibility, higher performance and faster development cycles, monolithic devices are giving way to modular chiplet-based systems built from specialized silicon components in a single package. UCIe, an open industry standard, allows system designers to combine specialized silicon in a single package instead of redesigning large monolithic SoCs or developing a new SoC for every application. This approach can reduce latency,2 power,3 size, development cost and complexity while accelerating time to market and giving designers greater flexibility to reuse proven silicon IP.

What’s the Role of AMD?

The semiconductor industry is entering a new era where innovation is increasingly driven by chiplet architectures that combine specialized chiplets to meet specific use cases. AMD Versal RF Series chiplets are uniquely positioned to be the starting point to harness UCIe connectivity, bringing heterogeneous compute architecture with up to 80 TOPS of DSP compute, integrated RF converters and SWAP-C benefits to customers and unlocking the next generation of adaptive RF systems.

What Do Versal RF Devices Support? AMD Versal™ RF Series devices will be the first Versal adaptive SoCs to enable UCIe 1.1 connectivity. They will support up to four independent UCIe-SP (standard-package) interfaces and up to two UCIe-AP (advanced-package) interfaces, providing multi-terabit per second aggregate in-package bandwidth. Additional AMD adaptive SoCs with UCIe support will be added as the market matures.

AMD Versal UCIe Infographic
Envisioned applications with commercial or custom UCIe chiplets: RF AFEs, AI, specialized compute, CPO / fiber.

What Makes Versal RF Series Devices Unique? Versal RF Series adaptive SoCs integrate high-resolution RF data converters, dedicated hard intellectual property (IP) for DSP, AI Engines and programmable logic in a single-chip device. They offer up to 80 TOPS (trillion operations per second) of heterogeneous DSP compute and significant SWAP-C (size, weight, power and cost) benefits by combining the functionality of six devices into a single package.

Adding UCIe connectivity will expand these capabilities significantly by allowing Versal RF Series chiplets to communicate directly with co-packaged chiplets optimized for specific workloads, such as:

  • Third-party RF AFEs or data converters

  • AI acceleration chiplets

  • CPUs

  • GPU specialized compute

  • Custom security engines

  • Communications processors

  • Application-specific ASICs

What Changes with Chiplets? Chiplets move specialized functions closer together. Historically, integrating RF front ends, AI accelerators, optical interfaces, memory subsystems or custom ASICs required board-level connections that can add latency, power consumption, size and design complexity. UCIe provides a standardized in-package interconnect, enabling efficient communication between heterogeneous chiplets, including silicon from different vendors.

Benefits of UCIe will enable customers to build customized systems leveraging existing, proven chiplets, eliminating time and helping lower the cost to redesign large monolithic SoCs. These benefits include:

  • High-bandwidth chiplet-to-chiplet communication

  • Reduced latency and improved power efficiency compared to AMD devices with board-level GTM2 serialized interfaces2 3

  • Reuse of proven silicon IP

  • Potential for lower development costs

  • Faster time to market

  • Design flexibility through chiplet integration

What’s Next? The introduction of UCIe connectivity for select Versal RF Series adaptive SoCs transforms the device into a scalable chiplet platform capable of serving a broad range of next-generation RF, AI, networking and communications applications and enables SWAP-C reduction. 

Production chiplets are expected to be available with select Versal RF Series devices in the fourth quarter of 2027.

© 2026 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, Versal, and combinations thereof are trademarks of Advanced Micro Devices, Inc. UCIe and Universal Chiplet Interconnect Express are trademarks of Universal Chiplet Interconnect Express, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective owners. Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with the system manufacturer for specific features. No technology or product can be completely secure.

  1. Based on AMD internal analysis. Select AMD Versal RF adaptive SoCs with support for UCIe 1.1 interfaces, as of August 2026. (VER-114)

  2. Select AMD Versal RF adaptive SoCs with support for UCIe 1.1 specification offer lower latency than AMD adaptive SoCs with support for board-level GTM2 serialized interfaces. (VER-115)

  3. Based on AMD internal analysis, comparing the estimated energy efficiency for select Versal RF Series adaptive SoCs with UCIe 1.1. SP and AP interface support, defined as the energy consumed in (pJ/bit) to traverse from FDI to bump and back to FDI, with all the adapter and physical layer-related circuitry including, but not limited to, Tx, Rx, PLL, clock distribution, etc., versus the estimated energy per bit consumed by AMD adaptive SoCs, with support for board-level GTM2 serialized interfaces. (VER-116)

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Source: AMD Chips and Compute · newsroom.amd.com

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