How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Angstroms

3D rendering of a self-aligned complementary field-effect transistor with vertically stacked NMOS and PMOS devices.

Sep 29, 2026

As the semiconductor industry pushes beyond the 10 angstrom (Å) node, traditional transistor designs are hitting fundamental scaling limits.
SEMulator3D® was used to validate a self-aligned complementary field-effect transistor (SA-CFET) approach, which could unlock the next era of chip performance, power efficiency, and design flexibility.

As their dimensions continue to shrink, conventional gate-all-around (GAA) nanosheet transistors may face growing challenges, such as leakage, mobility, resistance, and manufacturing variability.

A proposed self-aligned complementary field-effect transistor (SA-CFET) architecture addresses these constraints by vertically stacking N-channel metal-oxide-semiconductor (NMOS) and P-channel metal-oxide-semiconductor (PMOS) devices and using self-aligned modules to improve density and manufacturability.

What Is a CFET?

A complementary field-effect transistor (CFET) is a transistor architecture that vertically stacks NMOS and PMOS devices. This configuration can reduce cell area, increase effective channel width, and improve electrostatic control compared with side-by-side device layouts.

With SEMulator3D®, the Semiverse® Solutions team used digital twin process modeling to show that the self-aligned architecture can support static random-access memory (SRAM) and logic cells while delivering a 0.0094 μm² SRAM bit cell, a 52.7% area reduction compared with N3 technology, and at least a 10 nm overlay window across critical contact layers.

Why Transistor Scaling Beyond 10 Å Is Difficult

Many experts believe that the currently most-advanced transistor architecture, silicon GAA nanosheets, may begin to have physics and manufacturing issues past the 10 Å node. These challenges include:

Source-drain tunneling and increased leakage current as the gate length shrinks
Mobility issues, surface scattering, and manufacturing issues as the channel thickness is reduced
Contact and parasitic resistance issues as the transistor size decreases
Manufacturing variability that may seriously impact yield beyond the 10 Å node

With these challenges, it is becoming increasingly difficult to scale down the nanosheet device area or enhance device density by simply shrinking the active area, gate, or metal patterning pitch.

Why CFET Matters for Sub-10 Å Scaling

CFET architecture stacks PMOS and NMOS vertically to achieve significant area reduction, enhanced performance through larger effective channel width, and improved electrostatics.^1,2,3,4 However, CFET architecture faces its own critical integration challenges: metal gate isolation complexity and contact crowding that can cause electrical shorts or open circuits. These issues intensify at smaller dimensions, requiring innovative solutions for scalability.

How the Self-Aligned Architecture Works

To address these challenges, we propose a SA-CFET architecture with three key self-aligned modules: SA-BPR (buried power rail), SA-CT (contacts), and SA-TSV (through-silicon via).

These process modules enlarge the edge placement error window and mitigate contact crowding, improving process margin. The architecture uses non-metal gate cut design and middle dielectric isolation (MDI) for work function split.⁵ SA-CFET maintains compatibility with N3 specifications (42-nm CPP, 21-nm metal pitch), transforming overlay-sensitive steps into self-aligned processes for better manufacturability.

A screenshot of a computer AI-generated content may be incorrect. Process sequence for self-aligned CFET integration, including buried power rail, contacts, and through-silicon via

Figure 1. Key integration loops of the SA-CFET

Design Implementation: SRAM and Logic Cells

The SA-CFET design can be used to successfully build 6T SRAM cells and logic standard cells (NOT, NAND, NOR) with no metal gate split required within any single fin, simplifying the process flow. The complete interconnection network, validated through digital twin (process) simulation, demonstrates complex routing capability while maintaining self-aligned benefits.

Digital twin models of SA-CFET SRAM, NOT, NAND, and NOR interconnection networks

Figure 2. 3D interconnection network architecture showing SRAM and logic cells (NAND, NOR, NOT) with complex routing validated through digital twin simulation

Performance Results

SA-CFET achieves a 6T SRAM bit cell area of 0.0094 μm²—a 52.7% reduction versus N3 technology6 and 19% reduction versus state-of-the-art A7 CFET designs. Process robustness validation shows at least a 10-nm overlay window for all critical contact layers with no open/short failures, confirming robust process margin.

SRAM bit cell area comparison chart showing technology evolution from N3 FinFET to SA-CFET, with 52.7% area reduction versus N3 and 19% reduction versus state-of-the-art A7 CFET SA-CFET SRAM cell area compared with N3, N2, A10, and A7 technologies

Figure 3. SRAM bit cell area comparison showing 52.7% reduction versus N3 technology

Overlay-window validation for critical SA-CFET contact layers

Figure 4. Overlay window validation confirming robust process margin across critical contact layers

Conclusion

This article describes an innovative self-aligned CFET architecture that employs multiple self-aligned processes. Using this architecture, we designed a process sequence for both a 6T SRAM device and for logic standard cells using digital twin (process) modeling.

We found the proposed architecture shares similar or even more relaxed design rules compared to current or conventional semiconductor manufacturing. It also provides an area reduction from both existing N3 devices and state-of-the-art CFET architectures.

More importantly, it avoids many of the scaling issues found in existing nanosheet architectures, achieving enhanced performance through larger effective channel width and improved electrostatics at smaller nodes. We believe that this work demonstrates a potential architectural solution to support CMOS scaling for transistors at 10 Å and beyond.

References

S. Subramanian et al., "First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers," 2020 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, 2020, pp. 1-2.
A. Vandooren et al., "Monolithic-CFET with Direct Backside Contact to Source/Drain and Backside Dielectric Isolation," 2024 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2024, pp. 1-4.
H. Kükner et al., "Double-Row CFET: Design Technology Co-Optimization for Area Efficient A7 Technology Node," 2024 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2024, pp. 1-4.
A. Veloso et al., "Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster," 2021 Symposium on VLSI Technology, Kyoto, Japan, 2021, pp. 1-2.
H. Mertens et al., "Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning," 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023, pp. 1-2.
C. H. Chang et al., "Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond," 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 27.1.1-27.1.4.
T. -Y. J. Chang et al., "A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute," 2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2025, pp. 492-494.