Chip Industry Technical Paper Roundup: Oct. 13
Chip Industry Technical Paper Roundup: Oct. 13
Semiconductor Engineering collects multiple recent chip technology papers, covering spatially deterministic nucleation of 2D semiconductors from KAIST and other institutions, the Hyper-NA EUV lithography system with a numerical aperture of at least 0.75 from Zeiss SMT and ASML, and BARE-AI from the University of Florida and others, which uses built-in performance monitors to defend against bit-flip attacks in AI hardware.
M3D mem-TFT neuromorphic computing; 2D semiconductor nucleation; ultrathin high-κ dielectrics; hyper-NA EUV litho; bit-flip attack detection in AI accelerators; programmable DRAM controllers; foundry-compatible photonic bends.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Spatially deterministic nucleation of 2D semiconductors by etching flux | KAIST, TDS Innovation, Hanyang University, UNIST |
| Integration of high-κ oxide on 2D semiconductors with carbon-dot monolayer assembly as van der Waals interfacial layer | UIUC, National Energy Technology Laboratory, Argonne National Laboratory, Monash University |
| Hyper-NA: a system with a numerical aperture of at least 0.75 | Carl Zeiss SMT, ASML |
| BARE-AI: Bit-Flip Attack Resilience in AI Hardware through Built-in Performance Monitors | University of Florida, UT Dallas, RPI |
| Monolithic 3D integrated memristor-thin-film transistor for electrically programmable multimode reservoir computing | Seoul National University, Yonsei University |
| Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller | ETH Zürich, CISPA, New York University |
| Low-loss ultra-compact photonic bends with enhanced fabrication tolerance for commercial foundry processes | Georgia Tech |
Find more semiconductor research papers here.
Linda Christensen
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Linda Christensen is vice president of operations and a contributing writer at Semiconductor Engineering.
Source: Semiconductor Engineering Chips and Packaging · semiengineering.com