Semiconductor Engineering collects multiple recent chip technology papers, covering spatially deterministic nucleation of 2D semiconductors from KAIST and other institutions, the Hyper-NA EUV lithography system with a numerical aperture of at least 0.75 from Zeiss SMT and ASML, and BARE-AI from the University of Florida and others, which uses built-in performance monitors to defend against bit-flip attacks in AI hardware.
Research teams from Syracuse University, FAU, and TU Dresden published a paper on RAPID (Row-parallel Arithmetic Processing-In-DRAM), an architecture that performs row-parallel, bit-parallel computation directly inside DRAM.
Researchers from ETH Zürich, CISPA, and NYU have published a paper proposing the Terracotta framework, which simplifies deploying new DRAM technologies through a flexible DRAM interface and a programmable memory controller. The framework includes two components: a custom command extension allowing DRAM vendors to define new commands within a single standardized interface, and a programmable memory controller that system designers can program after tape-out to support new DRAM technologies. The paper is available on arXiv (number 2610.06475).
TrendForce's weekly report shows DRAM lead times have reached 20 weeks (versus a balanced level of 8 weeks), and the shortage is limiting the ability of some NAND vendors to support enterprise SSD solutions.