Row-Parallel DRAM Computing Cuts Data-Reorganization Overhead (Syracuse, FAU, TU Dresden)
Row-Parallel DRAM Computing Cuts Data-Reorganization Overhead (Syracuse, FAU, TU Dresden)
Research teams from Syracuse University, FAU, and TU Dresden published a paper on RAPID (Row-parallel Arithmetic Processing-In-DRAM), an architecture that performs row-parallel, bit-parallel computation directly inside DRAM.
Researchers at Syracuse University, Friedrich-Alexander-Universität Erlangen-Nürnberg, and TU Dresden published a technical paper titled “RAPID: Row-Parallel Arithmetic Processing in DRAM.”
Abstract Excerpt: “Processing-using-memory (PUM) architectures perform computation directly within DRAM to reduce costly data movement between memory and processors. Because charge-sharing operations are confined to individual bitlines, existing DRAM-PUM architectures reorganize data into column-oriented, bit-serial representations. This organization is fundamentally incompatible with the row-oriented, word-parallel layouts used by conventional processors and accelerators, requiring expensive data-layout transformations whenever computation transitions between PUM and conventional execution. In this paper, we present RAPID, a Row-parallel Arithmetic Processing-In-DRAM architecture. RAPID augments the DRAM subarray with two lightweight extensions: migration cells that enable localized horizontal data movement between neighboring bitlines and inversion cells that provide efficient in-array logical inversion. These primitives enable RAPID to operate directly on row-parallel, bit-parallel data, preserving CPU-compatible layouts while exploiting the massive parallelism of the DRAM subarray.”
Find the technical paper here. October 2026.
Tegge, William C., João Paulo Cardoso de Lima, Shouzhi Fang, Jeronimo Castrillon, and Alex K. Jones. “RAPID: Row-Parallel Arithmetic Processing in DRAM.” arXiv preprint arXiv:2610.02502 (October 2026). https://doi.org/10.48550/arXiv.2610.02502
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