Backside Clock Meshes Cut Skew and Power in 2nm Nanosheets (UCSC)
Backside Clock Meshes Cut Skew and Power in 2nm Nanosheets (UCSC)
A UC Santa Cruz team released the first design space exploration of backside clock meshes, implemented on OpenROAD and GT2N using a 2nm GAAFET BSPDN process. Backside power delivery provides thick, low-resistance metal layers on the wafer's backside, reducing clock skew and power; since flip-flops stay on the frontside, all connections run through silicon vias. The paper was released on arXiv in October 2026 (arXiv:2610.02401).
Researchers at the University of California, Santa Cruz published a technical paper titled “Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology.”
Abstract Excerpt: “Clock meshes are used in high-performance VLSI designs to minimize skew and tolerate on-chip variation, but they spend scarce routing resources on premium metal layers. Backside power delivery creates a new option: it adds thick, low-resistance metal layers on the back of the wafer, and the power grid does not consume all of them. Flip-flops remain on the frontside; a backside mesh therefore cannot drive them directly, and every connection passes through a through-silicon via. We present the first design-space exploration of backside clock meshes, implemented in OpenROAD on GT2N, a 2 nm nanosheet technology.”
Find the technical paper here. October 2026.
Ali, Wajid, Muhammad Hadir Khan, Dalton Gaddy, and Matthew Guthaus. “Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology.” arXiv preprint arXiv:2610.02401 (October 2026). https://doi.org/10.48550/arXiv.2610.02401
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