UCSC Publishes Paper on 2nm Backside Clock Grid Design
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In October 2026, a UC Santa Cruz research team published a paper on designing backside clock grids (backside clock distribution networks) for the 2nm nanosheet GAAFET process. According to Semiconductor Engineering, this is the first design space exploration for backside clock grids, based on a 2nm process with a backside power delivery network (BSPDN), implemented using the OpenROAD and GT2N tool flows. BSPDNs provide thick, low-resistance metal layers on the wafer's backside, helping reduce clock skew and power; however, since flip-flops remain on the wafer's front side, all clock connections must run between front and back through silicon vias. The paper was published on arXiv in October 2026 (arXiv:2610.02401). This is the only report on the matter so far, with no follow-up developments or conflicting information.
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- Semiconductor Engineering Chips and PackagingBackside Clock Meshes Cut Skew and Power in 2nm Nanosheets (UCSC)
A UC Santa Cruz team released the first design space exploration of backside clock meshes, implemented on OpenROAD and GT2N using a 2nm GAAFET BSPDN process. Backside power delivery provides thick, low-resistance metal layers on the wafer's backside, reducing clock skew and power; since flip-flops stay on the frontside, all connections run through silicon vias. The paper was released on arXiv in October 2026 (arXiv:2610.02401).