Skip to content

All AI news

Today 1 items
Oct 8Thu
  1. Semiconductor Engineering Chips and Packaging38

    Shift Left Complicates Fab Data Management

    Semiconductor fabs are using real-time equipment sensor data and AI/ML inference models to move yield anomaly detection inside process modules, accelerating yield learning and improving advanced process control (APC). Equipment sensor sampling has risen from about once per second to once every few tens of milliseconds, data types have grown at least 10x compared with a decade ago, and some fabs generate hundreds of petabytes per year. How to process data in sub-second timescales while preserving context and connectivity is the main data management challenge shift left brings.

  2. Semiconductor Engineering Chips and Packaging31

    Closing The Visibility Gap

    Every test, inspection and monitoring method for advanced chips has physical, spatial or temporal blind spots, and no single technology provides a complete picture. Vendors including Nordson, ZEISS and Teradyne note that defects such as solder voids and head-in-pillow can pass electrical test yet cause early failures, while X-ray still faces trade-offs among precision, throughput and resolution for stacked dies and TSV inspection.

  3. Semiconductor Engineering Chips and Packaging26

    Finding Critical Defects Before They Become Costly Failures: Process Control For Hybrid Bonding And Advanced Packaging

    In advanced packaging, defects accumulate value step by step through the process flow, and shrinking feature sizes push inspection requirements toward front-end levels, spanning surface particles, sidewall cracks, buried defects, microbump anomalies and bonding voids. Manufacturers need to combine complementary methods—high-sensitivity 2D inspection, infrared subsurface inspection and 3D metrology—in a unified workflow, balancing sensitivity with throughput, and use effective classification to turn inspection results into actionable process information.

  8. NVIDIA Blog72

    NVIDIA, Microsoft Kick Off a New Beginning for Windows PCs With RTX Spark and AI Agents

    NVIDIA and Microsoft announced at the Windows AI and Surface event in San Francisco that they are jointly building agent software and hardware for Windows PCs.

    Why it matters: The article details the specs and launch timeline for RTX Spark and DGX Station for Windows, helping readers assess how realistic running large models locally with resident agents will be.

Oct 7Wed
  2. Semiconductor Engineering Chips and Packaging20

    Blog Review: Oct. 7

    Semiconductor Engineering rounds up this week's blogs: a Siemens team explores how CFETs and buried power rails can shrink chip area and improve energy efficiency to meet the needs of AI accelerators, data centers, and mobile processors; Synopsys and Cadence analyze the collaborative advantages of agentic AI in EDA; Arm introduces the AMBA C2C extension for chiplet connectivity.

  3. TrendForce Insights Semiconductor Industry Insights44

    Passive Part, Active Battle: Inside CPO's FAU Coupling Bottleneck

    Precisely aligning and fixing fiber array units—FAU coupling—has become a critical bottleneck in CPO manufacturing and testing. At SEMICON Taiwan 2026, TSMC unveiled an upgraded COUPE roadmap: per-chip bandwidth reaching 3.2 Tbps in 2026, doubling to 6.4 Tbps in 2027, with a long-term target exceeding 51.2 Tbps. Integrating optics on the substrate can deliver a 4X power-efficiency gain, with OOI reaching 10X.

Oct 5Mon
  1. AMD Chips and Compute14

    AMD Helios: Designing and Building the Future of AI Infrastructure (Videos)

    AMD has released video resources related to AMD Helios AI infrastructure, along with brand assets including AMD trademarks and logos for download. Before downloading, users must accept terms and conditions: these AMD Marks may only be used in promotional materials featuring products with AMD CPUs, GPUs, APUs or FPGAs, and AMD may terminate the license at any time.

Oct 1Thu
Sep 30Wed
Sep 29Tue
  1. Lam Research Semiconductor Manufacturing Technology36

    Lam’s New Logistics Hub Built for Velocity, Resilience, and AI-Era Growth

    Lam Research has opened its largest US warehouse in Livermore, California—a 470,000-square-foot logistics and supply chain hub built to support semiconductor supply chain pressures driven by AI technology demand. A 40,000-square-foot automated storage and retrieval system with 15 robots cuts parts retrieval time from 6 minutes to under 30 seconds, 12 times faster than the existing system. The center is expected to support more than 200 jobs by 2027.

Sep 28Mon
Sep 24Thu
  1. TrendForce Insights Semiconductor Industry Insights43

    Why CSPs Are Turning to QLC SSDs for KV Cache Storage

    TrendForce has observed that some cloud service providers are adding QLC SSDs to SSD PODs, replacing the default TLC SSD plus HDD configuration. In AI inference, the Prefill and Decode stages repeatedly read and write KV Cache, and as context windows and batch sizes grow, KV Cache capacity needs multiply, prompting vendors to move caching from costly, capacity-limited HBM down to cheaper tiers.

Sep 23Wed
Sep 21Mon
  1. Marvell Optical Interconnect and Official Announcements43

    Marvell to Showcase Industry-First 2nm Optical Technology Demos for AI Data Center Infrastructure at ECOC 2026

    Marvell will present industry-first 2nm optical interconnect demonstrations at ECOC 2026 in Malaga, Spain, September 20–24, 2026, including the first 2nm 400G/lane optical PAM4, the first 2nm 800G ZR/ZR+ pluggable modules with MACsec (driven by the Libra 2nm coherent DSP), and the first 2nm 1.6T ZR and coherent-lite O-band demos.

Sep 17Thu
  2. AMD Chips and Compute26

    Building Infrastructure for an AI World in Motion

    At the AI Infra Summit, AMD argued that the core of AI infrastructure design should not be chips or networking but a system's ability to adapt to changing demands. The piece notes that agentic AI turns a single request into a multi-step chain of retrieval, tool calls, code execution and sub-agent coordination, and should be measured by cost per completed task rather than cost per token, offering three auditable principles: adaptable, economical, and open.

Sep 14Mon
  1. TrendForce Insights Semiconductor Industry Insights55

    Why 4hi HBM May Not Be the One-Size-Fits-All Fix

    TrendForce says 4hi HBM samples will enter supplier views in early 3Q26, with NVIDIA and other AI chip vendors evaluating low-stack configurations to cope with the HBM shortage. The spec has real use cases in edge AI scenarios like autonomous driving and robotics; SK hynix previously supplied HBM2E to Waymo in 2024 with automotive certification, but near-term demand contribution remains very low.

Sep 10Thu
  1. TrendForce Insights Semiconductor Industry Insights42

    Why Everyone Is Talking About Hybrid Bonding, and Who Is in the Race

    TrendForce takes a deep dive into 3D advanced packaging and hybrid bonding: TSMC's SoIC uses 3D interconnect with 56x the interconnect density and 5x the energy efficiency of CoWoS, entered mass production in 2025 with a 6µm bond pitch, and plans to shrink to 4.5µm by 2029; Intel's Foveros Direct, at a 9µm pitch, enters mass production in 1H26 with the Clearwater Forest Xeon 6+.

Sep 9Wed
Sep 8Tue
  1. Lam Research Semiconductor Manufacturing Technology28

    Why Panel-Level Processing Could Transform Advanced Semiconductor Packaging (Semi 101)

    AI's demand for larger, more complex chip packaging is pushing the industry to explore panel-level packaging (PLP): replacing round wafers with rectangular panels to improve area utilization and scalability beyond traditional wafer-level packaging size limits. Lam Research is advancing the technology toward production readiness through tool innovation and infrastructure investments, including the Salzburg Panel Center of Excellence. The technology still faces challenges in uniformity control, yield management, and industry standards.

Sep 2Wed
Sep 1Tue
Aug 31Mon
Aug 26Wed
  2. Lam Research Semiconductor Manufacturing Technology24

    Virtual Fabrication Meets Stress Physics: Solving GAA Channel Non-Uniformity

    Lam Research used SEMulator3D® integrated stress modeling to predict stress non-uniformity across GAA stacked nanosheet channels before fabrication — nFET stress differences reach 400–800 MPa, while pFET stays below 200 MPa. DOE experiments show that channel thickness, fin width, and lateral etch jointly affect stress uniformity, with increasing the topmost channel thickness from 4 nm to 7 nm significantly reducing the stress difference.

Aug 25Tue
Aug 18Tue
  1. TrendForce Insights Semiconductor Industry Insights38

    Advanced Packaging: Market Trends and Outlook

    TrendForce maps the latest landscape of 2.5D/3D advanced packaging in the AI chip supply chain: TSMC's 5.5x reticle CoWoS is in mass production with yields above 98%, with plans to expand beyond 14x after 2029; Intel's EMIB-T yields have improved significantly, expanding beyond 8x this year and over 12x by 2028, targeting customer mass production in 2027.

Aug 3Mon
  1. Marvell Optical Interconnect and Official Announcements26

    Marvell to Showcase Advanced AI Memory and Storage Infrastructure Portfolio for Agentic AI Inference at FMS 2026

    Marvell will showcase its AI memory and storage portfolio at FMS 2026 on August 4-6 at Booth #805, featuring PCIe 6.0 enterprise SSD controllers, CXL near-memory acceleration and memory pooling switches, CXL memory expansion cards, Octeon DPUs, and Photonic Fabric technology for optical interconnect scaling.

Jul 24Fri
  1. AMD Official Announcements69

    AAI 2026: AMD Delivers Full-Stack Compute for the Agentic AI Era

    At Advancing AI 2026 on July 23, AMD unveiled a full-stack AI and physical AI product portfolio, including its first rackscale solution, AMD Helios (72 Instinct MI455X GPUs plus 18 6th Gen EPYC "Venice" CPUs).

    Why it matters: The official announcement consolidates Helios rack, MI400 series CPU/GPU spec figures, and major customer deployment plans, allowing readers to benchmark actual progress against competing solutions.

Jul 22Wed
  1. TrendForce Insights Semiconductor Industry Insights46

    From Training to Inference: A Paradigm Shift in the Memory Hierarchy

    As test-time scaling rises, the AI industry's focus is shifting from training to inference, bringing structural changes to the memory hierarchy. In the first half of 2026, NVIDIA and Google respectively launched CMX, Rubin integrated Groq LPX, and the TPU v8i designed for inference (with 72 GB more HBM3e and 384 MB SRAM than the TPU v8t).