芯片行业本周回顾：GlobalFoundries 扩厂、CXMT 推进 DDR5 与 EUV、Teradyne 投资 FormFactor

Fab expansion accelerates; China advances memory and EUV; Teradyne’s test deal; SEMICON West and OCP highlights; 3D SiP; TSMC and ASML signals; 300mm fab spending; optical and 3D-compute startups raise fresh funding; quantum HW advances.

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Manufacturing and process technology

GlobalFoundries will operate two new fabs in Malta, New York, under a U.S.-Japan initiative involving up to $21B in investment. The first fab is expected to come online in 2029. GF also unveiled an FD-SOI roadmap for physical AI.
Applied Materials unveiled its $5B EPIC Center, a 600,000-s.f. semiconductor process and equipment R&D facility in Silicon Valley.
Infineon and Wolfspeed inked a new multi-year supply agreement for 200mm SiC wafers.
Nikon introduced a new lithography system for advanced packaging, offering 1.5 µm line-and-space resolution and 40% higher throughput than its predecessor, at 72 panels per hour. The maskless system supports large substrates and RDL patterning, with availability planned for April 2027.

Packaging and test

FormFactor and Teradyne will co-develop semiconductor test technologies for HBM, advanced packaging, silicon photonics, and HPC. Teradyne also agreed to invest $300M in FormFactor. Teradyne also introduced a semiconductor test platform for edge-AI chips.
ASE expanded its PowerSiP platform with a vertically integrated 3D packaging solution that places voltage regulation closer to AI processors, reducing parasitic routing losses by 50% or more to improve power efficiency in data centers and HPC systems.

China narrows the gap

CXMT reportedly plans to introduce a DDR5 server RDIMM using 4F² DRAM cells by year-end, potentially improving density and manufacturing costs. The development could help narrow China’s memory gap, although CXMT has not disclosed production yields, manufacturing volumes or evidence of cost competitiveness.
China-based Langdao Silex unveiled a prototype EUV light source with 90% localized components, reports SCMP. TrendForce says the source exceeds 15W output but remains far below commercial EUV power levels, with mass production still estimated to be three to five years away.
Nvidia’s AI-accelerator shipments in China fell 44% year over year in the first half of 2026, leaving it with 34% of the data-center AI-accelerator market by units shipped, compared with Huawei’s 28%, according to IDC data reported by Reuters.

Around the Valley

This week’s SEMICON West conference:

Synopsys CEO Sassine Ghazi said in a keynote address that autonomous chip design can already take some customer specifications to verified RTL, while physical implementation, verification and final sign-off still require human involvement.
Nvidia expanded its AI tools for semiconductor manufacturing, including the new cuPotential CUDA-X library for atomic-scale simulation. Lam Research plans to integrate Nvidia NanoVDB into SEMulator3D, which is expected to speed select wafer-etch modeling by up to 30x.
Siemens and Nvidia integrated cuLitho with Calibre to speed computational lithography, saying it’s up to 12x faster for full-chip OPC workloads. It supports High-NA EUV and curvilinear inverse lithography.

Fig. 1: Synopsys President/CEO Sassine Ghazi and Semiconductor Engineering’s Ed Sperling at SEMICON West this week. Source: G. Haley/Semiconductor Engineering

The OCP Global Summit was also held this week in San Jose. Find all the highlights in our New Technologies section below.

Earnings season heating up

TSMC reported Q3 revenue of roughly US$46.7B, up 41.2% year over year in U.S. dollar terms, with 2nm accounting for 8% of wafer revenue. CEO C.C. Wei said the company has seen “no sign of slowdown” in AI demand. But rising prices and macroeconomic uncertainty are weighing on consumer and other price-sensitive markets, prompting more cautious planning for 2027. TSMC also said it has discussed participating in Musk’s Terafab, but any fab collaboration would need to be operated by TSMC.
ASML reported record Q3 sales of €11.7B, up about 55% from a year earlier, and said planned supply for the next two years will not fully meet customer demand. The company is evaluating additional capacity beyond its previously planned expansion.

Market and investment

More than $8.5B in Q3 chip industry startup funding was tracked across 80 companies, with AI inference, memory alternatives, photonics, networking, and other data-movement technologies drawing some of the quarter’s biggest rounds.
SEMI projects global 300mm front-end fab equipment spending will rise 31% to $149B in 2026 and reach $227B by 2029, driven by AI, HPC and leading-edge semiconductor demand. Equipment investment in the Americas is expected to more than double from $18.1B in 2026 to $40.6B in 2029.

Fig. 2: SEMI 300mm Fab Outlook, Q326 update.

Big hauls

Salience Labs raised $125M to accelerate deployment of its optical circuit switching technology for AI infrastructure.
Mueon raised $65M to scale up its stackable, modular 3D platform that integrates compute, memory, interconnect, power delivery, and thermal management.

New Technologies

OCP Summit

Microsoft announced a new AI inference accelerator, slated for 2027, with an inference-first architecture optimized for long-context, memory-intensive, and decode-heavy AI workloads.
Intel detailed its latest GPU for AI inference, with a design supporting up to 480 GB of LPDDR5X memory.
Marvell announced six-channel CXL 3.2 memory expanders for AI inference, along with a 3.2T protocol-aware retimer and second-generation 1.6T AEC DSP.
Wiwynn, Ayar Labs, and GUC demonstrated a CPO compute system with integrated optical engines and system-level cooling.
Nvidia and Cisco announced plans for a new USFP optical module supporting 400Gb/s-per-lane signaling and up to 12.8Tb/s capacity.
Keysight introduced new 1.6T Ethernet test platforms, 1.6T copper interconnect validation, and a PCIe 7.0 protocol test solution. It also demonstrated multi-vendor Link Layer Retry interoperability.

Manufacturing and test

Siemens EDA introduced Tessent Silicon Executable software to deliver test patterns through PCIe and USB. Advantest and Teradyne are integrating it into their test platforms, as well as Simcenter SCADAS ES, a modular data-acquisition system for physical testing.
Particle Measuring Systems introduced a 20nm particle counter for inline monitoring of solvents used in semiconductor manufacturing.
IC-Link by imec and Polar Semi are collaborating on 8-inch enhancement-mode GaN manufacturing, using imec’s GaN-on-silicon technology for power devices.

Design, compute and power

IBM and Siemens EDA are collaborating on IBM’s nanostack transistor architecture, combining device research with EDA, process simulation, and lithography optimization for future manufacturing.
ChipAgents and Nvidia introduced a benchmark designed to test whether AI agents can carry an end-to-end digital chip-design task from specification through physical implementation and verified GDS.
Infineon added the XDP8HD40S-1, a new high-voltage hot-swap controller for digital power-path protection and monitoring, to its power semiconductor portfolio.
Rambus unveiled a PMIC designed for LPDDR6 SOCAMM2 server module chips for AI infrastructure, with advanced power conversion, sequencing, telemetry, and fault protection.
IBM plans to release an early research PDK for its 7-angstrom nanostack technology in Q1 2027, giving chip designers and EDA vendors an early way to explore design challenges for vertically stacked transistors.

Automotive

Microchip and Elektrobit introduced a pre-integrated AUTOSAR software stack for automotive processors.
TDK introduced two Hall-effect sensor ICs for motor-position sensing and xEV current sensing.

Global

Americas

Solstice Advanced Materials plans to expand its R&D in New York, including thermal management research.
Fujifilm will boost its Arizona production facilities for copper interconnect CMP slurries for advanced packaging and other applications.
SIA warns that U.S. chip production remains vulnerable to hidden upstream dependencies, with Tier 1 equipment and materials often relying on sub-tier raw materials and components at high risk of disruption, particularly rare earths and critical minerals.

Europe

Netherlands’ control over ASML’s advanced lithography technology gives it leverage in U.S.–China semiconductor competition, but that leverage is constrained by U.S. export controls, EU rules, security ties and commercial exposure to China, reports HCSS.
A CEPA analyst calls for the UK to strengthen its semiconductor industry by investing in Cambridge’s chip-design cluster and tapping pension funds for investment. It also recommends tighter scrutiny of foreign acquisitions and access to EU semiconductor pilot lines.

Asia

SK hynix is reportedly seeking U.S. approval to ship additional chipmaking equipment to its Dalian, China, fab, while conditioning a potential new U.S. NAND factory through Solidigm on that approval, according to Reuters.
NXP will receive a $250M loan from the EIB to expand operations in Malaysia.

Research

IBM Research developed an AI-agent framework for chip-design optimization that uses open-weight models and HLS feedback to explore hardware architectures. Applied to a quantum error-correction decoder, IBM reported a 52× HLS-estimated speedup for about $26 in inference cost; an all-proprietary configuration cost $299 and achieved a 204× speedup.

Oregon State, Yonsei, and Samsung researchers developed a laser-based method to characterize atomic defects in operating IGZO transistors. Testing devices fabricated under 25 processing conditions, the researchers identified oxygen-vacancy-related electron traps that affect threshold voltage, switching characteristics, and carrier mobility, potentially improving transistors for next-gen DRAM.

SUSTech and Tohoku University researchers developed high-performance p-type 2D transistors enabled by weak disorder engineering.

imec and Nvidia recapped their recent advancements using AI and accelerated computing for lithography, including AI-based CD-SEM denoising for sub-1nm and GPU-accelerated process-window OPC for High-NA EUV.

More academic papers

Agentic Systems in Chip Design Verification (Columbia, Google)
Understanding Power Consumption of Modern HBM (ETH Zurich, NYU)

Security

Hardware security advances

Marvell, Microsoft, and Oracle formed an OCP working group to standardize a NIST FIPS 140-3 Level 3 integrated hardware security module for hyperscale data centers.
Lattice introduced a PQC-enabled platform security stack for AI data centers with the latest version of Lattice Sentry.
SEALSQ plans to debut two quantum-resistant chips and a post-quantum ASIC design concept at electronica 2026.
KAIST researchers developed a programmable oxide transistor for time-based encryption that can reveal stored information after a preset delay or only at a designated time.
TU Darmstadt researchers proposed processor-level changes designed to remove sources of microarchitectural leakage that can undermine masked cryptographic software. The changes were integrated into an Ibex RISC-V processor, formally verified and evaluated on an FPGA.

AI Security

More than 400 scientists from 34 countries signed an open letter calling for stronger global AI security protections, including an international body to establish best practices for securing internet-connected AI models.
Anthropic published research suggesting small AI models could soon become capable of self-replicating on commercial IoT devices without relying on data-center infrastructure.

Hacks of the week

Backdoor hardware implants in Ledger signing devices sold through CryptoBilis reportedly enabled a $102M crypto theft.
Cyberattacks shut down supermarket refrigeration systems across France and the Netherlands by targeting internet-connected refrigeration controllers.
A hacker reportedly accessed Denmark’s civil registration system using a former employee’s leaked password, “123456,” exposing access to nearly 8.8 million personal identification numbers.
U.S. authorities arrested Canadian cybersecurity executive Edward Dubrovsky on extortion charges, amid the FBI’s crackdown on the ShinyHunters hacking group.

Security technical papers

Measurement Study of Backdoor Stealthiness (Radboud, Zagreb)
Lightweight Processor-Level Countermeasure Against Fault Injection (Mitsubishi)
ML-Assisted Power Side-Channel Attacks on ML Accelerators in Shared FPGAs (Yale & Northwestern)

Quantum Hardware

RIKEN, NTU, and ETH Zurich researchers demonstrated parallel control of five silicon spin qubits using a shared control line, achieving single-qubit gate fidelities above 99.99% during simultaneous operation of three qubits and above 99.9% during five-qubit operation. The approach addresses a key challenge in scaling silicon quantum processors.

IBM, Rutgers University, Ames National Laboratory, and collaborators demonstrated adaptive circuits on superconducting quantum hardware, using mid-circuit measurements and feedback to control chaotic quantum dynamics. The researchers observed a dynamical transition between quantum and classical behavior.

D-Wave delivered a 4,400-plus-qubit Advantage2 annealing quantum computer to Como, Italy, for installation as the country’s first annealing quantum computer.

New York University will establish a $284M quantum fab.

SkyWater and D-Wave extended their quantum manufacturing partnership, covering specialized semiconductor process development and manufacturing at SkyWater’s Minnesota fab.

Qilimanjaro Quantum Tech raised €19.6M (~$21.9M) to industrialize its analog and digital quantum computers.

Events and Webinars

Upcoming webinars are here, including:

Digital Twins and AI for Smarter Data Centers, Oct. 19 and 22
Introduction to PeakForce AFM-IR, Oct. 21
Infineon’s Solutions for High- to Low-Voltage DC-DC Applications, Oct. 21
Extended Analysis, Remote Access, and Connected Facility Monitoring, Oct. 22
Rambus Design Summit: Enabling Agentic AI, Oct. 22

Find upcoming chip industry events here, including:

Upcoming Events

PDF Solutions CONNECT: For Semiconductor Manufacturing Analytics and AI
Oct. 15–16 | San Francisco, CA

2026 EPEPS Conference: Electrical Performance of Electronics Packaging and Systems
Oct. 18–21 | Fort Worth, TX

Jasper User Group 2026: Cadence Connect
Oct. 21–22 | San Jose, CA

OktoberTech Silicon Valley
Oct. 22 | Mountain View, CA

Rambus Design Summit 2026: Enabling Agentic AI
Oct. 22 | Online

CASPA 35th Annual Conference and Dinner Banquet
Oct. 23–24 | Santa Clara, CA

IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE)
Oct. 27–29 | Phoenix, AZ

MICRO 2026: IEEE/ACM International Symposium on Microarchitecture
Oct. 31–Nov. 4 | Athens, Greece

IEEE Asian Solid-State Circuits Conference (A-SSCC 2026)
Nov. 1–4 | Taichung, Taiwan

PIC Summit Europe
Nov. 3–4 | Eindhoven, Netherlands

Siemens User2User Mid-Atlantic
Nov. 4 | Laurel, MD

SWTest Asia 2026
Nov. 5–6 | Hsinchu, Taiwan

ACM/IEEE ICCAD 2026
Nov. 8–12 | San Jose, CA

Electronica 2026
Nov. 10–13 | Munich, Germany

SEMICON Europe
Nov. 10–13 | Munich, Germany

GSA: 2026 WISH Conference
Nov. 10 | Santa Clara, CA

Electronic Specialty Gases & Systems Conference (ESGS)
Nov. 10–12 | Phoenix, AZ

SC26: International Conference for HPC Networking, Storage & Analysis
Nov. 15–20 | Chicago, IL

Hardwear.io Security Trainings and Conference NL 2026
Nov. 16–20 | Amsterdam, Netherlands

DVCon Europe
Nov. 17–18 | Munich, Germany

2026 SIA Awards Dinner
Nov. 19 | San Jose, CA