Researchers from Sandia National Laboratories and the Luxembourg Institute of Science and Technology published a paper that spatially resolves GAAFET leakage pathways using charge self-consistent Non-Equilibrium Green Function simulations based on the Contact Block Reduction method.
Researchers from Columbia University, Google DeepMind, and Google have published a paper proposing Back-to-the-Future (BTTF), an end-to-end agentic framework that automates post-simulation waveform debugging in chip verification.
Semiconductor Engineering collects multiple recent chip technology papers, covering spatially deterministic nucleation of 2D semiconductors from KAIST and other institutions, the Hyper-NA EUV lithography system with a numerical aperture of at least 0.75 from Zeiss SMT and ASML, and BARE-AI from the University of Florida and others, which uses built-in performance monitors to defend against bit-flip attacks in AI hardware.
Researchers from UIUC, NETL, Argonne National Laboratory and Monash University published a paper in Nature Communications using monolayer-assembled carbon dots to form an atomically thin van der Waals interface layer, enabling ultrathin high-κ oxides to be deposited on 2D semiconductors.
Researchers from KAIST, TDS Innovation, Hanyang University, UNIST and other institutions published a paper in Nature proposing an etching-flux-mediated single-nucleus nucleation method for 2D semiconductors that deterministically positions a single nucleation event at a designated location. Conventional strategies can only control nucleation density and achieve area-selective growth, but cannot determine where an individual nucleus lands within the growth area. Published in October 2026, the paper is open access.
Researchers from HUST, Hong Kong Polytechnic University, UCSB, and the National University of Singapore published a Nature Communications paper demonstrating high-performance ballistic-transport WSe2 monolayer p-type transistors via oxygen p-type doping. The approach solves insufficient doping and high contact resistance caused by MIGS from metal deposition, boosting p-type on-current, aiming to let 2D semiconductors surpass silicon at sub-1nm nodes for CMOS circuits.
A UC Santa Cruz team released the first design space exploration of backside clock meshes, implemented on OpenROAD and GT2N using a 2nm GAAFET BSPDN process. Backside power delivery provides thick, low-resistance metal layers on the wafer's backside, reducing clock skew and power; since flip-flops stay on the frontside, all connections run through silicon vias. The paper was released on arXiv in October 2026 (arXiv:2610.02401).