Chiplet 设计中即插即用原型验证如何加速：SignatureIP CEO 谈多裸片验证挑战

Accelerating Plug-And-Play Prototyping In Chiplet-Based Designs

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随着多裸片（multi-die）组装、共享资源和不同速度工具的引入，芯片验证难度显著上升，仅靠仿真已不够，需要结合仿真、emulation 与 FPGA 原型验证来确保系统按预期工作。SignatureIP CEO Purna Mohanty 谈及 chiplet 与共享内存资源的影响、多版本 I/O 的版本控制难题，以及硬件加速工具与实际设计速度不一致带来的工程挑战。

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Shared resources, a mix of tools running at different speeds, and multiple dies are adding new challenges for design teams.

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Verifying chips is becoming much more difficult in multi-die assemblies. Unlike in the past, when simulation was sufficient, designs now require a combination of simulation, emulation, and FPGA prototyping to ensure that entire systems will work as expected. Purna Mohanty, CEO of SignatureIP, talks about the impact of chiplets and shared memory resources, the challenges of version control across multiple flavors of I/O, and the challenges engineering teams face when hardware-accelerated tools are running at different speeds than the actual design.

Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.