超越 EPE 预算：构建下一代计算光刻

At the recent SPIE Photomask Technology + Extreme Ultraviolet Lithography conference, an expert panel discussed the growing importance of edge placement error (EPE). I had the pleasure of joining moderator Jed Rankin of IBM and fellow panelists Hans Stiepan of Carl Zeiss SMT, Ezequiel Vidal-Russell of Micron Technology, Jo Finders of ASML, Il-Yong Jang of Tekscend, and Vivek Balasubramanian of Applied Materials. Together, we brought perspectives spanning OPC and EDA, mask technology, lithography systems, materials, and metrology. One point quickly became clear: EPE is no longer a narrow lithography metric. It is becoming a system-level measure of how well our industry can translate design intent into a manufacturable, high-yielding device. The mask, scanner, resist, etch process, metrology, OPC, and downstream integration all contribute. Each discipline can optimize its own part, but a collection of local optima does not automatically produce the best device—even if everyone arrives with an excellent slide explaining why their part is already optimized.

EPE has become a system problem

As pitch scaling becomes more difficult, tighter control of placement, variability, and pattern fidelity becomes one of the main paths to continued scaling. The challenge is that EPE is an unbounded budget. Mask three-dimensional effects, absorber profile, sidewall angle, critical-dimension uniformity, registration, scanner behavior, resist variability, etch, stochastic effects, process-induced stress, and even wafer or die bonding can all move an edge or change its electrical consequence. Yet the audience survey delivered a wonderfully familiar verdict: OPC was viewed both as a major source of EPE and as the leading place from which future EPE reduction would come. In other words, OPC was cast as both the villain and the superhero. Jed leaned into the joke, asking what Ezequiel and I would need from the rest of the industry to carry that superhero burden. By the final poll, confidence in OPC had risen to 58 percent—prompting the prediction that I might appear next time in tights. I am happy to accept the confidence; the cape may be negotiable.

The EDA challenge: Stop treating residual error as one big bucket

Today, many effects that are difficult to isolate are absorbed into empirical corrections, rule tables, or an “etch” term. This is pragmatic and often necessary in production, where repeatability, runtime, yield, and schedule outweigh a perfect explanation. Ezequiel captured the dilemma well: after seeing the poll, he was not sure whether the OPC community should feel encouraged or concerned. The audience clearly expected OPC to take care of every systematic and correctable effect—and, where possible, reduce sensitivity to the uncorrectable ones too. That is an impressive job description for any superhero. But even OPC needs good physics, good data, and a process window; it cannot leap an inaccurate model in a single bound. As tolerances shrink, the effects we sweep into the correction bucket become large relative to the remaining process window. EDA must therefore represent the real manufacturing system more completely: not an idealized mask with uniform properties, but pattern-dependent mask profiles, realistic metrology behavior, scanner effects, process variability, and the interactions among them.

Not more data, better data

More data alone is not the answer. We need data that is physically meaningful, sufficiently repeatable for manufacturing, and connected to the patterns that matter on the wafer. A single SEM image contains far more information than one extracted CD. Contours, profiles, roughness, placement, local geometry, and pattern context can all inform better models. At the same time, no fab can measure everything. OPC and process models should help identify the patterns with the highest wafer sensitivity, rank the hotspots, and translate that sensitivity into mask and wafer metrology requirements. This closes a critical loop: modeling guides measurement, measurement improves modeling, and both focus resources on yield-relevant problems.

AI must be paired with physics and validation

I believe artificial intelligence will deliver one of the largest future gains in EPE reduction. Machine learning can capture residual systematic behavior that is difficult to model directly, while agentic systems can coordinate optimization across traditionally separate domains. But semiconductor manufacturing cannot rely on an unexplained black box. A model that reports zero EPE without showing why it is trustworthy is not production-ready. The path forward is explainable AI anchored by rigorous simulation, validated against appropriate metrology, bounded by known physics, and monitored for the conditions in which it can safely be applied.

Agentic systems should solve defined engineering problems

Agentic AI should not be turned loose across the ecosystem with the assumption that it will discover a global optimum on its own. Adoption will begin with well-defined problems: reducing global CDU, selecting robust mask geometries, optimizing source and mask together, prioritizing metrology, or connecting pattern variation to electrical impact. For each problem, we must define the objective, the data required, the knobs the system may turn, the physical constraints, and the validation criteria. Confidence will grow locally, and successful agents can then be connected into broader workflows.

EDA must connect EPE to power, performance, area, cost, and yield

Our customers do not sell EPE; they sell products defined by power, performance, area, cost, and yield. Some EPE limits are hard geometric boundaries: exceed them and a structure shorts, opens, or fails. Other errors occupy a gray zone where their importance depends on device behavior. EDA has an opportunity to bridge that gap by bringing electrical simulation, stochastic analysis, lithography, mask optimization, process modeling, and design technology co-optimization into a common decision flow. The goal is not simply the smallest geometric error everywhere. It is the right allocation of process margin where it creates the greatest product value.

Fig. 1: Process simulations using stochastic modeling techniques can predict process characteristics that lead to electrical problems with a design before reticles are built.

Collaboration is the path from local to global optimization

Foundries and IDMs sit at the center of this opportunity because they see the complete manufacturing flow and hold the data that connects mask, scanner, process, device, and yield. EDA providers need deeper partnerships with them, as well as with mask makers, metrology suppliers, and lithography equipment providers. Those partnerships must enable secure, purposeful sharing of data and context—not data collection for its own sake. The highest-value collaboration will define common EPE frameworks, expose the relevant process sensitivities, prioritize the dominant contributors, and establish closed feedback loops at the stage where each error can still be understood and corrected.

A practical direction for the industry

• Build fuller physical representations. Model pattern-dependent mask structure, process interactions, stochastic behavior, and time-dependent change rather than hiding them in a single residual term.
• Make metrology model-driven and device-relevant. Use OPC and simulation to identify sensitive patterns, then measure the locations and attributes that most strongly affect wafer performance.
• Combine AI with rigorous simulation. Use machine learning to capture residuals and accelerate prediction, while physics-based models provide explainability, boundaries, and validation.
• Apply agentic systems to bounded problems first. Define the target, inputs, controls, and success criteria before expanding across workflows.
• Optimize for product outcomes. Connect EPE decisions to power, performance, area, cost, yield, and manufacturability.
• Close loops across the ecosystem. Align EDA, mask, metrology, scanner, foundry, and IDM teams around common definitions and prioritized contributors.

The EPE era will last for decades

EPE scaling is not a temporary phase. As the industry moves from planar scaling to three-dimensional integration and eventually to time-dependent, system-level optimization, the definition of EPE will continue to evolve. Wafer-to-die bonding, new device architectures, curvilinear masks, high-NA lithography, and tighter coupling between manufacturing and electrical performance will create new correction and optimization problems. The opportunity for EDA is to become the connective intelligence across these domains—combining physics, data, and purposeful AI to turn fragmented process knowledge into manufacturable outcomes. The audience may be ready to call OPC the savior of EPE, and I appreciate the vote of confidence. But the real superpower will come from giving OPC better mask knowledge, better metrology, better process context, and tighter links to device performance. That is how we extend scaling: not by asking one team to wear the cape, but by enabling every part of the ecosystem to work together.