2026年Q3初创公司融资盘点：AI芯片与光互连主导，80家公司共融资超85亿美元

AI dominated funding in the third quarter of 2026, with two inference companies each announcing $1 billion in funding. But with the data center buildout driving insatiable demand for memory, investors also rewarded startups with alternatives to costly, capacity-limited HBM. Some are building on commodity DRAM or holding models in on-chip SRAM, while others stack memory directly onto compute.

Data movement at all levels of the stack remains a critical bottleneck, too. Interconnect technologies, networking chips, and photonics were the most active areas of the quarter, with startups tackling the problem with diverse approaches ranging from manufacturing-ready co-packaged optics, millimeter-wave RF signals over plastic waveguides, and ferroelectric glass modulators to optical couplers printed directly onto chips and coherent DSPs designed specifically for AI optics.

Nearly $7.5 billion of the quarter’s total was directed to just 22 startups that raised $100 million or more, including eight that saw investors return within roughly a year, some more than doubling the previous round. Plus, agentic EDA and AI-generated analog layout, small chip fabs, diamond-based defect inspection, large-area nanoimprint lithography, and memory-safe microcontrollers feature in this look at 80 companies that collectively raised over $8.5 billion in Q3 2026.

• Summary table
• Chips
• AI hardware
• EDA
• Manufacturing & equipment
• Test, measurement & inspection
• Memory & storage
• Photonics & optics
• Previous reports

Chips

Xsight Labs raised over $300.0M in funding led by Fidelity Management & Research Company with participation from Aliya Capital Partners, Atreides Management, Artisan Partners, Battery Ventures, Diagonal Capital, Intel Capital, Key1 Capital, Maverick Capital, Sienna Venture Capital, T. Rowe Price, Union Group, and Valor Equity Partners. Xsight Labs designs fully programmable data processing units (DPUs) and Ethernet switches for hyperscale, edge, and AI data center networks. Built on open standards, its DPU runs native Linux, DPDK, and SONiC and uses 64 Arm Neoverse N2 cores that sit directly in the data path to process millions of connections per second at full 800 Gbps line rate. The company’s 12.8 Tbps Ethernet switch operates at deterministic, sub-700ns latency under 200W. Funds will be used to accelerate the company’s roadmap, add support for emerging Ultra Ethernet Consortium standards, hire, and scale manufacturing. Founded in 2017, it is based in Tel Aviv, Israel.

Celero Communications raised $275.0M in Series C funding led by Atreides Management, Valor Equity Partners, and CapitalG, with participation from Sutter Hill Ventures and Maverick Silicon. Celero develops coherent DSPs for AI optical interconnects. Rather than adapting a long-haul coherent design, the company built a DSP architecture optimized for low power and low latency, paired with new analog circuitry connecting the DSP to the optical system that it says is designed to scale to higher bandwidth over multiple generations. The architecture targets scale-up, scale-out, and scale-across connectivity from 1.6T to next-gen 3.2T. Celero has validated 2nm coherent DSP silicon, including the DSP processing and analog technology. Funds will go to accelerating the product roadmap, R&D, and production readiness. Founded in 2024, it is based in Irvine, California, USA, and has raised $415M to date.

Cornelis raised $205.0M in funding. Cornelis builds scale-out networking for AI and HPC, spanning SuperNICs, switches, and open-source software built around its own switch silicon. Its 400 Gb/s system uses credit-based flow control and fine-grained adaptive routing, which the company says makes the fabric lossless and congestion-free. The company is sampling an 800G SuperNIC that supports Omni-Path, RoCEv2, and Ultra Ethernet concurrently. Cornelis is extending into scale-up networking with programmable in-fabric compute built on UALink and ESUN, an approach it says lets the network offload collective operations. Funds will be used to scale production. Founded in 2020 as a spin-out of Intel’s high-performance interconnect business, it is based in Wayne, Pennsylvania, USA.

Eliyan raised $145.0M in Series C funding led by Seligman Ventures, with participation from Cisco Investments, Lumentum, and other new and existing investors. Eliyan develops die-to-die, chip-to-chip, and rack-to-rack PHY and chiplet interconnect technology designed for AI systems with advanced package-level integration, multi-package scale-up architectures, memory expansion, and emerging high-bandwidth infrastructure fabrics. Available for both standard and advanced packaging, the protocol-agnostic PHY supports BoW and UCIe as well as simultaneous bidirectional signaling, which transmits and receives on the same wire at once to double bandwidth per interface. For die-to-memory applications, the company says its PHY delivers the bandwidth requirements for HBM on standard organic packaging with 90um and above bump pitch. Funds will be used to develop next-generation interconnect products, scale manufacturing, and expand into electro-optical interconnects. Founded in 2021, it is based in Santa Clara, California, USA.

Delos Data raised over $100.0M in funding from Matrix Partners, Playground Global, Socratic Partners, Capricorn Investment Group, Matter Venture Partners, IAG Capital Partners, and others. Delos Data builds a reference architecture for composing AI inference clusters from mixed hardware, models, and topologies, with a data interface between every endpoint. The interface silicon comes in three multi-protocol form factors: a 30+ Tbps I/O chiplet for GPUs, XPUs, and accelerators; 10+ Tbps near-packaged optics; and a 400+ Gbps card for CPUs, flash, and memory. Sitting between each endpoint and the network, it can detect failures first and manage recovery in hardware. A disaggregated scale-up server is planned to sample at the end of 2026. Funds will be used to hire and accelerate product development and sales. Founded in 2025, it is based in Palo Alto, California, USA.

Efficient Computer raised $97.0M in Series B financing led by TQ Ventures, with participation from Eclipse Capital, Union Square Ventures, Giant Ventures, Triatomic Capital, TO Capital, TF Capital, Mana Ventures, Toyota Ventures, Overmatch, and Borderless. Efficient builds a general-purpose processor based on a software-reconfigurable spatial dataflow architecture with a tiled grid of reconfigurable processing elements. The company claims the architecture delivers a 10× improvement in energy consumption for general-purpose computation, including AI. Its compiler, a drop-in replacement built on LLVM and MLIR, translates C and C++ into statically scheduled dataflow graphs placed and routed onto the grid. The processor, now in volume production, is aimed at physical AI, space and defense, and wearable devices. Funds will be used to ship the processor in volume and scale the architecture to data center-class performance. Founded in 2022, it is based in Pittsburgh, Pennsylvania, USA, and has raised $173M to date.

Point2 Technology added $60.0M to its Series B round led by LB Investment, joined by Arm, Maverick Silicon, and others, bringing the round to $136M. Point2 develops RF and mixed-signal interconnect SoCs and smart retimers for AI data center scale-up. Its technology transmits data using millimeter-wave RF transmitter/receiver SoCs through a plastic dielectric waveguide, avoiding both the skin effect that limits copper at multi-terabit speeds and the DSP and optical-electrical conversion required by optical cabling. A purely electrical technology, the dielectric waveguide can be deployed for 800G/1.6T/3.2T cable speeds and beyond by implementing modern modulation techniques for wireless transmission. Funds will be used to hire and to commercialize active RF cables and near-packaged and co-packaged modules. Founded in 2016, it is based in San Jose, California, USA.

OXMIQ Labs raised $35.0M in Series A funding led by Fundomo and Samsung Catalyst Fund, with participation from MediaTek, AM Intelligence Labs, Pegatron Venture Capital, CDIB-TEN, Darwin Ventures, Morgan Creek Digital, and others. OXMIQ provides GPU IP that integrates a CUDA-compatible GPU engine, a tensor processing engine, and an orchestration RISC-V CPU engine responsible for coordinating workloads and agents across the system. Designed for near-memory compute, the architecture is scalable from single-core AI deployments to large-scale data center configurations. OXMIQ’s chiplet integration architecture combines heterogeneous compute chiplets and memory in a single package that can be configured across logic process nodes, memory types, interconnect standards, and advanced packaging options. The startup also provides a software stack spanning high-level orchestration to low-level kernel optimization. Founded in 2023, it is based in Campbell, California, USA, and has raised $60M to date.

Celera Semiconductor raised $30.0M in Series B funding fully funded by Maverick Silicon. Celera develops custom analog ICs using an AI-powered, automated development flow that runs end-to-end from specification to architecture, IP provisioning, synthesis, verification, layout, and tapeout. The platform combines a library of digital twins of analog functions with behavioral modeling, synthesis, verification, and layout algorithms, targeting mixed-signal and PMIC designs on industry-standard silicon processes. Celera recently acquired SiliconGate, a provider of power management design services. Founded in 2018, it is based in Santa Clara, California, USA.

SCI Semiconductor raised £5.0M (~$6.8M) in funding led by PXN Ventures and Mercia Ventures, with participation from Osney Capital, Black Opal Ventures, and private investors. SCI Semiconductor builds memory-safe RISC-V microcontrollers based on CHERI, embedding security in the architecture by dividing memory into trusted compartments with tightly controlled access. Security features include referential integrity, spatial memory safety, and call gates, with deterministic use-after-free protection and lightweight compartmentalization of the RTOS. Funds will be used to step up production and develop next-gen chips. Founded in 2022, it is based in Sheffield, UK.

AI hardware

Etched raised $1.0B across two rounds, a $300.0M round in July led by Sequoia Capital and an additional $700.0M in August led by Jane Street. Additional investors include Andreessen Horowitz, Kleiner Perkins, Tiger Global, Bain Capital Ventures, Neo, Stripes, Primary, Positive Sum, Diffusion, Argo, Blackstone, SK Hynix, and individual investors. Etched co-designs chips, packages, PCBs, cold plates, interconnects, and manufacturing methods for rack-scale frontier model inference. Its architecture can operate the chip’s math blocks at reduced voltage, which the startup claims lets it run trillion-parameter sparse MoEs at 80%+ peak FLOPs without thermal throttling. Etched also uses a hybrid HBM/SRAM subsystem with a shared memory pool across an entire cluster, enabled by an ultra-low-latency, high-bandwidth interconnect to speed memory access across chips. Its first silicon was built on TSMC N4P, and the company has shipped its first rack. Funds will be used to scale production and customer deployments. Founded in 2022, it is based in San Jose, California, USA.

SambaNova raised $1.0B in the first close of a Series F round led by General Atlantic, with significant investment from Seligman Ventures and T. Rowe Price Associates, joined by A&E Investment, Assam Ventures, Battery Ventures, BlackRock, Cambium Capital, Intel Capital, Kabila Capital, QFO Capital, Qatar Investment Authority, Vista Equity Partners, and Volantis. SambaNova designs inference chips and systems based on its reconfigurable dataflow unit (RDU) architecture. Instead of operating kernel-by-kernel, the RDU chains operations into a streaming pipeline across a grid of programmable compute units and SRAM programmable memory units, fetching data for the next operator while the current one executes. A three-tier memory of on-chip SRAM, HBM, and DDR keeps models and KV cache close to compute. The company’s fifth-generation chip scales up to 256 RDUs, which SambaNova says supports models of up to 10 trillion parameters. Funds will be used to expand capacity, accelerate product innovation, and scale deployments. Founded in 2017, it is based in San Jose, California, USA.

Positron AI raised up to $875.0M across Series C and Series C-1 funding, a $375.0M Series C co-led by NEA, Atreides Management, Valor Equity Partners, Andra Capital, and SemiAnalysis Capital, and a Series C-1 of up to $500.0M led by NEA and individual investor Jim Clark. Additional investors include DFJ Growth, Qatar Investment Authority, Resilience Reserve, Arena Private Wealth, Natural Capital, Helena, 1517 Fund, Flume Ventures, Unless, Boardman Bay Capital Management, Fincadia Advisors, Banyan Ventures, and U First Capital, alongside strategic investors VentureTech Alliance, Hudson River Trading, Cisco Investments, and Naver Ventures. Positron builds memory-first AI inference systems on commodity LPDDR5X rather than HBM, and says its next-generation systems realize more than 90% of available memory bandwidth. Its next-generation accelerator pairs a reconfigurable systolic array, with weight memory co-located at each processing element, with 288 GB to 2.3 TB of memory per chip. The company claims a system combining four to eight of these chips can serve models beyond 16 trillion parameters and context windows beyond 10 million tokens in a single node. The accelerator is slated to tape out on TSMC N3P at the end of 2026, with production planned for the second half of 2027. Funds will support the tapeout, an engineering data center and emulation platform, and the system’s production ramp. Founded in 2023, it is based in Reno, Nevada, USA.

OLIX raised $312.0M in Series B funding from Fundomo, Arm, Hudson River Trading, Hummingbird Ventures, Crane Venture Partners, Plural Platform, Creandum, Phoenix Court, Transition Ventures, and individual investors. OLIX is designing AI inference hardware that uses specialized chips for each stage of the token production process. The system is built around a ‘slow and wide’ optical interconnect for die-to-die data movement, enabled by rack-scale co-design of every part of the link, including the SerDes and laser’s atomic structure, and workload scheduling using a fully deterministic compiler. The startup’s initial chip is a decode accelerator that holds a model in SRAM and is designed without advanced packaging or HBM. Funds will support planned delivery of the chip in the second half of 2027. Founded in 2024, it is based in London, UK.

SiMa.ai raised $150.0M in Series C funding co-led by Fidelity Management & Research Company and Amplify Partners, with participation from Alter Venture Partners, Dell Technologies Capital, Maverick Capital, +ND Capital, Point72, and StepStone Group, and joined by AllianceBernstein, Baron Capital, J.P. Morgan, and State of Michigan. SiMa.ai builds a machine-learning SoC that runs entire multimodal pipelines, from sensor capture and preprocessing through vision encoding and large multimodal models, on a single chip with no external accelerators. The company says it delivers 50 TOPS at under 10W across CNN, ViT, LLM, and LMM workloads. An open-source agentic software environment compiles ONNX models for the chip and orchestrates inference across the host and the SoC. SiMa.ai claims its next-generation hardware will deliver 1,000 dense TOPS and plans to ship it in H1 2028 for drones, humanoid robotics, and automotive ADAS and cockpits. Funds will be used to scale the software environment and develop next-gen silicon. Founded in 2018, it is based in San Jose, California, USA, and has raised $500M to date.

HyperAccel completed a KRW 150.0B (~$111.0M) second closing of its Series B round. HyperAccel designs LLM processing unit (LPU) IP and chips for transformer inference that use LPDDR5X memory instead of HBM. The LPU uses tens of large, coarse-grained programmable cores that each execute the full transformer computation, with a streamlined dataflow that reuses model parameters between cores to cut data movement. The startup says its server LPU, a 4nm SoC with eight LPDDR5X channels, averages 90% hardware utilization during the entirety of inference. A smaller appliance LPU has taped out. Funds will be used for mass production and hiring. Founded in 2023 as a KAIST faculty startup, it is based in Seoul, South Korea.

Velaura AI raised $110.0M in Series A funding led by Seligman Ventures, with participation from Capricorn Investment Group, Mayfield, Maverick Silicon, MARA, Premji Invest, Samsung Catalyst Fund, and StepStone Group. Velaura is developing ultra-low-power digital chip IP and a design platform for data center XPUs and physical AI. The startup says its proprietary low-voltage advanced node libraries and physical design methodology reduce the energy required for matrix multiplication operations and can be integrated into existing SoC architectures while maintaining full functional equivalence. Founded in 2022 as Auradine, it is based in Santa Clara, California, USA.

Quadric added $16.0M to its Series C round in a second close led by International Finance Corporation, with participation from Pear VC, Uncork Capital, BEENEXT Capital Management, and Offline Ventures, bringing the round to $46M. Quadric designs programmable AI inference processor IP that also runs classic DSP and control algorithms. Its general-purpose NPU (GPNPU) uses a hybrid Von Neumann and 2D SIMD architecture that executes matrix, vector, and scalar operations in a single pipeline, removing the need for a companion CPU or DSP. Because the core is C++-programmable rather than fixed-function, new operators and models are delivered as software updates without silicon changes. The company says the architecture scales from 1 to over 3,200 TOPS in multi-chiplet configurations, supporting convolutional and transformer models from computer vision to on-device LLMs and vision-language-action world models. Funds will be used to hire. Founded in 2017, it is based in Burlingame, California, USA, and has raised $90M to date.

EDA & design

ChipAgents added $60.0M in a Series A2 round from B Capital, Bessemer Venture Partners, Micron Technology, MediaTek, Ericsson, ScOp Venture Capital, and other existing investors. ChipAgents offers an agentic AI chip design environment with domain-specific agents capable of independently planning and executing multi-step design and verification workflows. The platform transforms specifications and code into production-ready RTL, verification assets, and automated root-cause analysis across digital, analog, and 3D-ICs, an approach the company claims reduces design cycles by over 50%. Funds will be used to scale deployments, hire, and accelerate product development. Founded in 2024, it is based in Santa Clara, California, USA, and has raised more than $134M to date.

Astrus raised $12.0M in Series A funding led by Caffeinated Capital, with participation from Khosla Ventures, Garage Capital, MVP Ventures, and RiSC Capital. Astrus builds AI software that automates analog layout. Its system adapts the approach behind AlphaGo, combining reinforcement learning, deep learning, self-play, and search in a loop designed to generate and evaluate trillions of layouts. Astrus claims it can generate tapeout-ready layouts that balance performance and manufacturability. Its first focus is the analog circuits behind high-speed SerDes, and the startup says the architecture is built to scale across circuits, technology nodes, and foundries. Funds will be used to commercialize the technology and hire. Founded in 2022, it is based in Toronto, Ontario, Canada.

Mach42 raised $9.5M in pre-Series A funding led by IP Group, joined by BGF and Foresight Group. Mach42 develops physics-driven surrogate modeling technology for analog circuit verification. The startup claims its surrogate models execute up to 2,500 times faster than conventional techniques and can handle complexity ranging from a few tens of ports up to analog subsystems with more than a thousand ports. The models can be automatically exported in Verilog-A, System Verilog, and C/C++ formats for compatibility with SPICE simulators. Funds will be used to hire and accelerate commercial adoption. Founded in 2019, it is based in Oxford, UK, and Palo Alto, California, USA.

VerifAIX raised $5.0M in seed funding co-led by Bluehill VC and Endiya Partners. VerifAIX develops a spec-first, agentic AI platform for hardware verification that combines AI with formal methods. It audits architecture and micro-architecture specifications against RTL to flag contradictions, ambiguities, and missing cases, then distills them into a formally grounded model of the design that the verification team reviews and approves. Specialized agents work from that shared model to generate test plans, coverage models, UVM/SystemVerilog testbenches, assertions, and checker logic, and drive existing simulation and formal tools to closure by triaging counterexamples and targeting coverage gaps. VerifAIX says every generated artifact traces back to a specification requirement. Funds will be used to develop the platform, strengthen its formal verification and simulation capabilities, and hire. Founded in 2024, it is based in Cupertino, California, USA.

Manufacturing & equipment

Fab2 raised $500.0M in Series A funding led by Fundomo, joined by Corner Capital, Paradigm, Duquesne Family Office, Maverick Silicon, StepStone Group, Protagonist, UDC Ventures, and an angel investor. Fab2 builds and mass-produces small chip fabs. The company designs the hardware and software needed to make chips and builds the fabs, tools, and components itself, including pumps, valves, sensors, nanometer-precision actuators, and boards. Fab2 also offers an in-browser collaborative EDA tool. Founded in 2023 as Atomic Semi, it is based in Austin, Texas, USA.

Morphotonics closed over $35.9M in an expanded Series B round from 3M Ventures, Innovation Industries, BOM, Invest-NL, European Innovation Council Fund, Ernij Next, and European Investment Bank. Morphotonics develops large-area nanoimprint lithography platforms that replicate micro- and nanoscale structures across large substrates. Its roll-to-plate process uses a cylindrical roller carrying a flexible stamp to progressively imprint nanostructures into UV-curable resin on panels. The resin is then hardened with UV light, an approach the company says reaches nanometer-scale resolution on substrates that scale beyond standard wafer sizes. Target applications include high-volume waveguide manufacturing, displays, and photonic components including co-packaged optics. Funds will be used to increase production capacity, advance product development, and hire. Founded in 2014, it is based in Veldhoven, the Netherlands.

SweGaN raised $14.0M in Series B funding led by Thisbe AB, North Ventures, and existing shareholders. SweGaN manufactures custom gallium nitride on silicon carbide (GaN-on-SiC) epitaxial wafers for RF and power devices used in telecom, defense, and satellite communications. Its approach utilizes a ‘transmorphic heteroepitaxy’ process where vacancy ordering is involved to perfectly transform the in-plane lattice atomic configuration from the SiC substrate to the AlN nucleation layer. The company says its QuanFINE structure combines the strengths of GaN and SiC without the conventional thick C-/Fe- doped buffer layer, bringing the hot channel closer to the heat-sink SiC substrate, reducing the buffer-related traps, and using the ultra-wide-bandgap AlN nucleation layer as an effective back-side barrier. Funds will be used to expand production capacity, hire, and accelerate R&D. A spin-off from Linköping University founded in 2014, it is based in Linköping, Sweden, and has raised $41M to date.

Nexstrom raised $12.0M in seed funding led by Xora Innovation, with participation from Foothill Ventures and SEEDS Capital. Nexstrom is developing a wafer-scale platform for growing single-crystal 2D transition metal dichalcogenide (TMD) semiconductors, which it says support precise electron control, reduce energy loss at the transistor level, and improve efficiency, while remaining compatible with advanced foundry manufacturing. The full-stack platform integrates CVD hardware, process technology, and wafer-scale 2D material growth into standard fab workflows, targeting continuous single-crystal growth on industry-standard 12-inch wafers. The company says it has achieved commercial-grade TMD synthesis on 300mm wafers and delivered wafer samples. Funds will support platform development, foundry collaborations, and hiring. Founded in 2024, it is based in Singapore and has raised $15M to date.

nanoSkunkWorkX closed the $2.0M first tranche of its seed round led by Tin Men Capital. nSWX engineers thin material interfaces, starting with a graphene-enabled interface for selected package-level copper routes in AI and HPC chip packages, intended to reduce electrical loss and improve heat spreading. It forms the interface with a process that uses electricity and liquid chemistry to build thin, structured layers at low temperature within existing manufacturing flows. Funds will be used for package proof structures, thermal and electrical validation, reliability testing, larger-wafer process development, and partner pilots. Founded in 2019, it is based in Petaling Jaya, Malaysia.

Test, measurement & inspection

QuantumDiamonds raised €91.0M (~$104.1M) between a €15M equity round led by World Fund and joined by Bayern Kapital, IQ Capital, Earlybird, First Momentum, UnternehmerTUM, Creator Fund, and Onsight Ventures and €76M in government backing from the German Federal Ministry for Economic Affairs and Energy and the Free State of Bavaria. QuantumDiamonds makes semiconductor inspection equipment that uses atomic-scale defects in synthetic diamonds to detect magnetic fields. Its first commercial system enables non-destructive 3D current imaging at the nanoscale, pinpointing the precise location and depth of chip defects. The technology is capable of detecting shorts, leakages, and opens in fine detail and at high speed with up to a 3 x 3mm field of view. It can operate in a wide range of temperatures. Funds will be used to deliver lab systems to chipmakers and advance wafer-level capabilities for high-throughput fab inspection. Founded in 2022, it is based in Munich, Germany.

Memory & storage

Kepler Computing emerged from stealth with $468.0M in funding. Kepler is developing memory designed for AI that it claims approaches the bandwidth per watt of SRAM while targeting up to 10× the capacity of HBM. Instead of relying on EUV, the company stacks novel low-voltage, CMOS-compatible devices on top of transistors to raise memory density, and uses 3D integration to place memory closer to compute. The memories are designed to serve as HBM and SRAM tiers in mainstream digital compute architectures. Kepler has its own dedicated 300mm fab and plans to sample its first AI memory product in 2026, with production in 2027. Founded in 2019, it is based in San Jose, California, USA.

TeRAM emerged from stealth with $37.0M in seed funding co-led by Primary Venture Partners, B Capital, Hyperion, and SemiAnalysis Capital, joined by Alumni Ventures and Lightscape Partners. TeRAM develops custom 3D SRAM for AI deployments ranging from data centers to edge devices. Its memory and packaging technologies integrate 3D SRAM directly onto AI compute chips, an approach the company says is designed to provide high bandwidth at low power under demanding thermal conditions. It tailors capacity, bandwidth, form factor, and packaging to minimize power consumption for each customer’s solution. The company is targeting initial production in 2029. Funds will be used to validate the technology, hire, and build custom chips. Founded in 2018, it is based in Los Altos, California, USA.

Photonics & optics

Lumilens emerged from stealth with $700.0M in Series C funding led by Atreides Management, Bain Capital Ventures, Meritech, Seligman Ventures, and Spark Capital, with participation from Addition, Aiconic Ventures, Alkeon, EDBI, Harbourvest, J.P. Morgan Private Capital, Lingotto, Mayfield, MVP Ventures, Qualcomm Ventures, Peak XV, Redpoint Ventures, Seifdune, and Thomvest Ventures. Lumilens designs and manufactures co-packaged optics, near-packaged optics, and pluggable optical transceivers for scale-up and scale-out AI data center networks. Each product is built on a unified technology platform spanning silicon photonics, mixed-signal ICs, electrical-optical interposers, and optical systems. The startup has also developed an electrical-optical interposer technology that simplifies photonic chip assembly. Founded in 2024, it is based in San Jose, California, USA, and has raised over $900M to date.

Ayar Labs raised an additional $150.0M in funding. Ayar Labs develops co-packaged optics (CPO) that connect thousands of GPUs across racks into a single cluster over an optical fabric. Its silicon photonics optical engines use microring modulators and integrate into system-in-package designs through a standard UCIe interface. An external laser source in the ELSFP form factor powers them, disaggregating the laser from the optical engine, an approach the company says improves thermal efficiency and serviceability. The startup also claims up to 10× higher bandwidth and 10× lower latency than copper and pluggable optics. Funds will be used for product development, validation, manufacturing scale-up, and a design center in Bengaluru, India. Founded in 2015, it is based in San Jose, California, USA.

iPronics raised $125.0M in Series B funding co-led by Maverick Silicon and Light Street Capital, joined by NVIDIA, with participation from Triatomic Capital, Bosch Ventures, Catalight Capital, European Innovation Council Fund, The Tate Family Trust, Fine Structure Ventures, Amadeus Capital Partners, Build Collective, Criteria Venture Tech, and other new and existing investors. iPronics develops a rack-mounted optical circuit switching (OCS) platform built on silicon photonics that provides programmable optical connectivity within and across racks, letting AI clusters reconfigure connectivity in real time for training and inference workloads. Its solid-state 32+ port scalable architecture has no moving mechanical switching elements, and integrates SOA gain control, optical power monitoring, streaming telemetry, and APIs, with a custom PDK optimized for low optical loss and crosstalk. Funds will be used to scale operations, accelerate commercial deployment, and hire. A spin-off from Universitat Politècnica de València founded in 2019, it is based in Valencia, Spain, and has raised $177M to date.

Polaris Electro-Optics raised $50.0M in Series B funding led by Walden Catalyst Ventures, with participation from Socratic Partners, Cambium Capital, Knollwood, Hudson River Trading, Koch Disruptive Technologies, M Ventures, Rhapsody Venture Partners, Buff Gold Ventures, and Blue Sky Capital. Polaris develops electro-optic modulators based on a proprietary ferroelectric nematic glass that exhibits a strong Pockels effect. The material is applied to finished silicon photonic wafers after they leave the foundry, using standard processes with no poling. The company claims its modulators reach 400 Gbps per lane at sub-volt drive voltages, and says the material’s electro-optic response can be tuned from 200G toward 800G per lane. Funds will be used for portfolio expansion, volume scale-up, product tapeouts, qualification, and hiring. Founded in 2021 as a spin-out from the University of Colorado Boulder, it is based in Carlsbad, California, USA.

Quintessent raised $40.0M in Series A funding led by Cycle Capital, joined by Goldman Sachs XIG-Industry Ventures, Hina Liberty Capital, Susquehanna International Group, InterVest, Safar Partners, Ciena, Foothill Ventures, M Ventures, Osage University Partners, and Sierra Ventures. Quintessent offers a single-chip quantum dot-based dense wavelength division multiplexing (DWDM) comb laser for optical scale-up networks. Built with gallium arsenide O-band quantum dot gain material heterogeneously integrated on standard silicon photonics, the product generates eight precisely spaced wavelengths from a single laser with a single bias control. The startup says its laser architecture is designed to reduce power consumption, simplify manufacturing, and improve reliability. Funds will be used for product maturation and development of other optical components. Founded in 2019, it is based in Goleta, California, USA.

Lightspring raised €3.1M (~$3.6M) in seed funding led by Atlantic VC and OVNI Capital, joined by Concept Ventures, IXCORE GROUP, Plug and Play, and industry angels. Lightspring uses 3D lithography to fabricate optical links, including waveguides and free-space optics, directly onto photonic chips in a single process step with no pre-alignment, for fiber-to-chip, laser-to-chip, and chiplet-to-chiplet coupling. Each structure is written at under 0.1 micron tolerance and automatically aligned, and the startup is targeting coupling losses under 0.5 dB with two-week design cycles. Lightspring is aiming for large-scale manufacturing by 2030. Founded in 2026 based on research from Institut FEMTO-ST, it is based in Besançon, France.

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