PVTW：将芯片表征从 PVT 扩展到真实工作负载

For decades, silicon characterization has been built around Process, Voltage, and Temperature, or PVT. We characterize devices across process variation, sweep voltage and frequency, control temperature, generate SHMOO plots, and establish the operating envelope of the silicon.

That methodology remains fundamental. But today’s high-performance processors are increasingly systems in their own right. An AI accelerator may contain thousands of compute elements, distributed SRAM, high-speed SerDes, PCIe and Ethernet interfaces, multiple clock and power domains, advanced packaging, firmware, operating systems, compilers and application software.

Two devices operating at exactly the same voltage, frequency, and temperature can behave differently depending on what they are being asked to do.

This suggests adding another dimension: PVTW: Process × Voltage × Temperature × Workload

Frequency can be swept within this characterization space to determine operating margin.

The objective is not to replace traditional ATE characterization with System Level Test. It is to combine the electrical precision and control available from ATE with the realistic operating environment available from SLT, while retaining the ability to use either independently.

One platform, two capabilities, three modes

One way to implement PVTW is through a hybrid characterization architecture integrating ATE resources and SLT capability.

There is no reason to recreate resources that already exist in ATE. Existing ATE infrastructure, including older generation platforms, can provide programmable device power supplies, individual rail control and measurement, variable frequency clocks, digital stimulus and capture, ATPG and structural content, parametric measurements, and conventional SHMOO characterization.

SLT provides something fundamentally different: the application environment.

The processor can boot firmware and an operating system, load drivers and runtime software, and execute deterministic workloads designed to exercise specific parts of the architecture. For an AI processor, those workloads might emphasize compute, SRAM, external memory, PCIe, Ethernet, or chip-to-chip communication. Other workloads could intentionally activate several simultaneously to create realistic system stress.

The architecture therefore provides three modes. ATE mode performs conventional electrical, structural, and parametric characterization. SLT mode executes controlled system workloads. Combined mode uses ATE resources to control and measure electrical conditions while the device executes an SLT workload.

Combined mode is where PVTW becomes particularly interesting.

From conventional SHMOO to workload SHMOO

Consider a conventional voltage and frequency SHMOO using ATPG or appropriate functional content. At a controlled temperature, establish the operating boundary.

Now boot the processor, establish a deterministic workload, and repeat the sweep.

Start with a compute-intensive workload. Repeat with SRAM, external memory, PCIe, and Ethernet-intensive workloads. Finally, create combinations that deliberately generate simultaneous compute, memory, and I/O activity.

Suppose an ATPG SHMOO indicates that a device operates correctly down to 0.72 V at a particular frequency, while an SRAM-intensive application begins producing errors at 0.76 V.

That 40 mV difference is not simply a disagreement between ATE and SLT. It is characterization information.

Something about the workload is consuming margin. Is it SRAM timing? Clock distribution? IR drop? Simultaneous switching noise? A thermal gradient? Power delivery? Or an interaction among several subsystems?

Characterization requires control

There is an important distinction between testing and characterization.

Booting Linux, running an AI workload, and observing whether the processor crashes is useful testing. Characterization requires controlled variables, repeatability, and the ability to deliberately move the operating boundary.

Hold workload, temperature, and frequency constant while sweeping a selected voltage rail. Then hold workload, temperature, and voltage constant while sweeping frequency. Change temperature and repeat.

The hybrid architecture can go deeper. Hold I/O and memory rails constant while margining the core rail during a compute workload. Then margin a memory-related rail while executing a memory-intensive workload.

We can begin creating subsystem-specific workload SHMOOs that connect:

• Workload → Subsystem → Electrical Margin

From workload failure to electrical debug

Consider a device that passes Wafer Sort and Final Test but develops errors after a sustained application workload. Cooling reduces the failure rate, while increasing the core voltage does not eliminate the problem. Telemetry indicates that most errors are associated with the same memory interface or byte lane, although the failing addresses move.

The device does not necessarily have to leave the characterization platform.

SLT mode can expose the system behavior and help isolate the subsystem. The platform can operate in ATE mode to investigate electrical and structural characteristics using programmable power, clock control, ATPG, functional patterns, and parametric measurements.

Or both capabilities can operate together. The workload can reproduce the marginal condition while ATE resources manipulate selected rails and clocks.

The three modes therefore answer different questions. SLT exposes the behavior. ATE investigates the electrical and structural characteristics. Combined mode characterizes their interaction.

This creates a tight engineering loop:

Create workload → Observe marginality → Isolate subsystem → Characterize electrically → Modify conditions → Repeat workload → Establish correlation → Determine root cause

For me, that is the interesting possibility behind PVTW. SLT no longer needs to be viewed only as a downstream production screen. Combined intelligently with ATE resources, it can become part of a controlled silicon characterization environment.

But this leads to another question. If two devices both PASS, are they actually equivalent?

That is the subject of Part 2: Beyond Pass/Fail: Characterizing Silicon Margin with PVTW.