Chip Industry Week In Review

Nvidia faces questions about security and oversight; 300mm SiC breakthrough; Siemens buys Lauterbach; chiplet standards; new memory bets; imec interposer process flow; TPUs with CPUs; 2D transistors; anti-smuggling tools for chips.

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Innovations

A wave of announcements this week, including several from SEMICON Europa and electronica 2026 in Munich, highlighted advances in semiconductor manufacturing, advanced packaging, automotive chips, and AI hardware.

Manufacturing and test

Infineon reported an industry-first milestone in 300mm silicon carbide manufacturing, fabricating functional power devices at its Villach, Austria fab using existing silicon processing equipment. The larger wafers can accommodate 2.3 times as many chips as 200mm wafers, potentially lowering manufacturing costs for automotive, industrial, and AI data center power devices.
imec completed baseline process flows for its NanoIC silicon-interposer platform, including TSVs and multiple routing layers for chiplet and 3D integration. A silicon-interposer PDK is planned for early 2027.

Chips and systems

AMD introduced its 6th-gen EPYC server and embedded processors, including models for semiconductor ATE; an AI GPU with 288GB of HBM4; and tamper-resistant FPGAs for security-critical systems.
Arm introduced the Cortex-M42 processor to bring ML and DSP capabilities to cost- and area-constrained intelligent endpoints in a compact, AHB-based design.
Google added two new 8th-gen TPU systems: TPU 8i Max for massive context windows and higher rack compute density, and TPU 8tx for secure and confidential inference. TPU 8tx pairs Google accelerators with AMD EPYC CPU hosts.

Fallout continues after Nvidia CEO Jensen Huang’s resignation:

Congressional investigations: Senators are seeking the preservation of records related to chip exports and Megaspeed, calling for tighter AI-chip export controls. House committee leaders also requested a closed-door Nov. 18 briefing from Huang.
Inaction questioned: President Trump authorized tougher action on suspected Nvidia chip diversion three times this year, but Commerce Secretary Howard Lutnick resisted over concerns that tighter restrictions could escalate trade tensions with China, Axios reported. Separately, Nvidia general counsel Tim Teter contacted a senior Commerce Dept. official in late summer 2025 seeking information about the Megaspeed chip-smuggling investigation, indicating Nvidia’s legal leadership was aware of the investigation before the current scandal. The company subsequently characterized its Megaspeed dealings as “normal.”
Circular financing: Nvidia’s web of financial ties across the AI industry is facing fresh scrutiny after Huang’s resignation. The Financial Times says Nvidia made more than 120 investments this year and held or committed about $124B in equity investments by July, raising questions about whether its aggressive dealmaking and financing of companies that buy its chips will continue without him.
Policy fallout: The episode has renewed debate over export-control enforcement and Chinese intelligence targeting of U.S. technology companies, with CFR highlighting enforcement gaps and CSET urging scrutiny without overreaction.

Deals and funding

Siemens plans to acquire Lauterbach, a provider of hardware-assisted debugging and real-time trace tools for embedded software and complex SoCs. The deal is expected to close in H1 2027.
Mitsui Chemicals confirmed it will acquire JSR in a transaction valued at approximately ¥1.84T ($11.9B), combining two major Japanese materials suppliers, including JSR’s photoresist and advanced materials businesses.
TSMC approved investments of up to $1B in OpenAI and Anthropic, allocating up to $500M for each, plus a separate $500M investment company focused on the semiconductor ecosystem.
Fractile raised $720M to develop frontier AI chips that stack DRAM directly on top of logic to speed up output token generation.

Memory

Samsung Electronics broke ground on a previously announced HBM advanced-packaging facility in Asan, South Korea, accelerating the planned start of production by a year to June 2028.
TSMC is reportedly considering 3D DRAM production at Nvidia’s request, potentially through new capacity or an acquired fab. Still, TSMC said that it remains focused on its core logic foundry business.
Vertical Compute and imec expanded their collaboration to integrate magnetic memory directly above 16nm logic.
Winbond approved NT$73.1B (US$2.2B) in spending to expand its 300mm memory fab in Kaohsiung, Taiwan.

Reports and analysis

Lowy Institute estimates U.S. AI data centers have nearly 40 times China’s computing power, with U.S. AI chips providing about 31 times the compute. China, meanwhile, leads in critical-mineral production and downloads of open AI models.
CSIS says Chinese rare-earth shipments to the U.S. remain about 75% below pre-restriction levels, despite agreements intended to restore supply. U.S. chipmakers have also faced scandium shortages and delays in obtaining Chinese export licenses.
Counterpoint Research says soaring memory prices are driving up smartphone costs, with memory now accounting for 54% of a low-end phone’s bill of materials, up from 20% in Q3 2025. Prices are expected to keep rising through Q1 2027.

Chiplet standards and interoperability

The UCIe Consortium published UCIe 4.0, which takes the specification beyond chiplet-level interfaces to the integration of multiple chiplets into an on-package system. New features include an on-package memory link between SoCs and memory logic chiplets, co-optimized link profiles with improved energy efficiency, and enhanced manageability, security, and reliability.
ASRA and imec released requirements for interoperable automotive chiplets, covering connectivity, power management, and functional safety.

Results

Year-over-year revenue change: Applied Materials Q4 up 53%, Infineon Q4 up 19%, Onto Innovation Q3 up 88%, Silicon Labs Q3 up 22%, SMIC Q3 up 34%, and TSMC October revenue up ~60%.
Latest chip stock moves are here.

Fig.1: Jochen Hanebeck, CEO of Infineon Technologies, with the 300mm power SiC wafer.

Quick Links To More News

In-Depth — Low Power-High Performance and Test, Measurement and Analytics newsletters; the optical superhighway for AI.

Global — Europe’s SiC, photonics and fab investments; Asia memory and packaging; U.S. diamond semiconductors.

New Technologies — Design and test tools; KrF lithography and materials repair; edge AI accelerators; high-power ATE; GaN EV charging.

Security — Chip smuggling countermeasures; recruiting ex-intelligence operatives to combat espionage; AMD processor vulnerabilities; HW security research.

Trending Video — LPDDR6 becomes an essential ingredient as intelligence moves into autonomous and mobile edge systems.

Research — 2D transistors; ferroelectric memory; room-temperature materials processing.

Quantum Hardware — Next-gen QPUs; chiplet-based quantum processors; silicon-spin computing; photonic chip advances.

Workforce | Education — OPT fee pushback; new semiconductor STEM and training programs; Qualcomm layoffs in India.

Events and Webinars — SC26 in Chicago; Hardwear.io Netherlands; DVCon Europe; GaN, computational lithography, SEM and HPC webinars.

Global

Europe

Cadence will make EDA and systems tools available to European chip startups and SMEs through EuroCDP.
onsemi canceled a SiC manufacturing expansion in the Czech Republic.
Nexperia is seeking $2B in damages from Chinese parent Wingtech and related parties, alleging harm to its business.
CEA-Leti and ISRL launched SubFAB Labs in Grenoble, a platform for testing technologies that reduce the environmental impact of chip manufacturing.

Asia

Vishay and Kaynes plan to establish a back-end manufacturing joint venture in India covering post-fabrication wafer processing, assembly, test, and packaging.
Mitsui Kinzoku plans to invest ¥190B (~US$1.2B) in a new copper foil plant in Malaysia for high-frequency circuit boards.
Paras Semiconductors and BroadPak are partnering on an advanced-packaging OSAT facility in Madhya Pradesh, India.

Americas

LLNL and Diamond Quanta are collaborating to use pulsed laser annealing to reduce defects in diamond for high-power electronics, with plans for a pilot manufacturing platform in Petaluma, California.

New Technologies

Design, verification and test

Accellera published the Portable Test and Stimulus Standard (PSS) 3.1, adding enhancements that improve model reuse, constraint expressiveness, software integration, target-code generation, and coordination across increasingly complex hardware and software execution environments.
Teradyne introduced its Omnyx Edge inline board-test system for physical and edge AI applications, designed to improve test coverage and manufacturing efficiency for increasingly complex electronic assemblies.
Siemens announced a toolkit for signal and power integrity verification of boards and electronic systems that combines domain-specific AI agents for SerDes, DDR, signal integrity, and power integrity analysis with physics-based simulation.
Cadence launched a connected design environment for boards and electronic systems that unifies schematic design, component discovery, expertise, and procurement for individual engineers and small design teams.
Keysight’s photonic design software added support for Tower Semiconductor‘s PH18 silicon photonics PDKs.
Synopsys supplied Infineon with a virtual development tool to support digital twin engineering for Infineon’s new MCUs for advanced automotive and physical AI applications.

Lithography and materials

Canon introduced a new KrF lithography scanner for memory and logic chip manufacturing. Scheduled for launch in early December, the system offers throughput of up to 400 300mm wafers per hour and 4.0 nm overlay accuracy. It also accommodates wafer warpage of up to 700 microns, addressing manufacturing challenges associated with 3D device structures and wafer bonding.
Hummink introduced its BIRD module for micron-scale material deposition and defect repair using maskless capillary printing and local laser sintering.

AI and compute

Expedera and Cadence teamed up to demonstrate an edge AI subsystem in pre-silicon simulation, pairing Expedera’s NPU and Cadence’s AI co-processor and distributing workloads for execution across both IP blocks.
MemryX AI released a new AI accelerator with a distributed dataflow architecture designed to support larger models across edge devices, industrial systems, and high-density inference infrastructure.

Automotive and power electronics

Keysight expanded its high-power ATE portfolio to support applications operating at up to 1,500V, including power-stage characterization, battery testing, charging systems, power conversion, and aerospace equipment.
Infineon, Visteon, and Shinry are collaborating to develop an efficient single-stage onboard charger for EVs built with GaN BDS technology.

Research

2D transistors

NUS-led researchers developed wafer-scale, single-crystal gate dielectrics for 2D transistors, integrating titanium dioxide (TiO₂) with MoS₂ and WSe₂ channels. The devices achieved near-ideal switching, minimal hysteresis, and inverter static power consumption below 1 picowatt, potentially enabling ultra-low-power logic chips.
Tsinghua University researchers developed a room-temperature process for depositing gate dielectrics for 2D transistors using a clay-based material. The process avoids high-temperature annealing after dielectric deposition and enables MoS₂ transistors operating at 1 volt with hysteresis as low as 1 millivolt. The team also demonstrated logic gates and SRAM, suggesting a potential route to lower-temperature chip fabrication.

Researchers at UW–Madison, Texas A&M, and the U.S. Army Research Lab developed nonvolatile memory devices based on sliding ferroelectric tunnel junctions. Using atomically thin molybdenum disulfide and engineered gold contacts, the devices achieved a reported 100,000-fold improvement in memory readout contrast, potentially enabling more energy-efficient memory.

University of Rochester and Technion researchers developed a method for altering molybdenum’s crystal structure at room temperature using precisely controlled mechanical pressure. The technique creates new crystal grains without heating the metal to approximately 1,000°C, potentially enabling localized defect repair and improved materials for future semiconductor interconnects.

Security

Alerts and vulnerabilities

AI, chip and tech companies are recruiting ex-intelligence operatives to combat espionage risks in the wake of former Nvidia CEO Jensen Huang’s affair with an alleged Chinese spy, Reuters reported.
AMD disclosed three side-channel vulnerabilities in 5th-generation EPYC processors that could expose sensitive data. Google Cloud has implemented protections between virtual machines but says customers need OS updates to address attacks within them.
AMD also issued security bulletins covering firmware, UEFI/SMM, IOMMU, and transient-execution vulnerabilities, including a RowHammer attack targeting SEV-SNP memory protections.
Intel disclosed multiple UEFI firmware vulnerabilities affecting its D50DNP and M50FCP server boards, along with TDX Migration Trust Domain flaws that include a critical authentication vulnerability. Intel released updated firmware and MigTD 0.7.2 to address the issues.

New offerings

Google DeepMind developed an agentic formal-verification framework that proved key security properties of Signal’s cryptographic implementation down to the compiled machine code running on devices. DeepMind says the approach eventually could be applied to systems such as medical-device firmware and power-grid software.
AWS launched Nitro Sandboxes, adding hardware-isolated environments and cryptographic attestation for AI workloads.
IBM and Cisco announced plans to embed Anthropic’s Claude Mythos cybersecurity model into their security products.
Lattice and NXP released a joint secure computing solution for industrial edge AI applications.

Government security news

ENISA released a new report on the state of cybersecurity in the EU, evaluating regulatory compliance, cybersecurity system maturity, and future resilience across each member state.
French security officials blame Iran for cyberphysical attacks that shut down refrigeration systems at more than 700 retail sites nationwide last month, but didn’t assign blame for the second wave of attacks that hit refrigeration systems across 11 European countries on Nov. 2.
President Trump nominated Palantir security chief Michael LoSapio to serve as the next CISA director, pending Senate confirmation.
CISA’s alerts for the week are here.

Security technical papers

Texas A&M researchers proposed a 5G-based location-verification system for AI accelerators to help combat chip smuggling and enforce semiconductor export controls. Called 5G CATS, the architecture would combine a 5G radio, cryptographic engine, and hardware interlock within the GPU package to verify chip locations and restrict unauthorized operation. Simulations showed improved detection of attempts to disguise a chip’s location using long-distance fiber relays.

And:

Sensor-to-Register Data Protection for Resource-Constrained RISC-V Devices (Durham)
Protection Through Bounded Delegation in RISC-V MCUs (Minho, Infineon)
Private Boosted Decision Trees Ready for Trusted HW & Leakage-free Hyperparameters (Luebeck, ETH Zurich)

Quantum Hardware

IBM announced its upcoming quantum processor, which will be built to execute 10,000 quantum operations across 520 programmable qubits, with plans to link two into a single system.

Rigetti Computing reported 99.5% median two-qubit gate fidelity on its 108-qubit superconducting processor, built from 12 interconnected nine-qubit chiplets. Internal testing also showed 99.7% median fidelity across a 50-qubit subset, demonstrating progress in modular QPU performance.

Diraq deployed what it calls the first silicon-spin quantum computer in a commercial data center, installing an eight-qubit system at Equinix in Sydney, Australia. Built using conventional semiconductor manufacturing processes, the system draws less than 20 kW, with plans to scale to 256 qubits within a year.

Xanadu and HyperLight built a TFLN optical switch with an insertion loss of 7 mdB, a nearly 3× improvement over the companies’ previous effort to reduce qubit signal degradation in quantum photonics.

Workforce, Education

The SIA urged the Department of Homeland Security to withdraw proposed fees for Optional Practical Training (OPT), warning they could hurt U.S. semiconductor recruitment and manufacturing. The proposal would impose a $70K initial fee and $30K for subsequent OPT periods, including STEM extensions. SIA asked for exemptions for semiconductor and other critical-technology workers if the rule moves forward.

SEMI Foundation launched its global Chip the Future Challenge, inviting students to submit semiconductor research or develop solutions in chip design, manufacturing, AI hardware, advanced packaging and emerging technologies.

Lam Research Foundation partnered with LEGO Education on a hands-on STEM initiative designed to spark student interest in engineering and technology.

Qualcomm reportedly began layoffs in India, with around 1,000 jobs potentially affected.

Events and Webinars

Upcoming webinars are here, including:

Accelerate Your GaN Design, Nov. 17
AI-Driven Computational Lithography, Nov. 17–18
Modernizing USB 2.0 for Edge AI and AI PCs, Nov. 17
Coupling the SPH Solver w/Fidelity Flow for Rain Simulations, Nov. 18
Advances in In-Situ SEM Nanomechanical Characterization, Nov. 18
Point-of-Load Regulation for HPC and Telecom, Nov. 19
Resilient Electrical Systems for Data Centers, Nov. 19

Find upcoming chip industry events here, including:

Upcoming Events

SC26: International Conference for HPC Networking, Storage & Analysis
Nov. 15–20 | Chicago, IL

Hardwear.io Security Trainings and Conference NL 2026
Nov. 16–20 | Amsterdam, Netherlands

DVCon Europe
Nov. 17–18 | Munich, Germany

2026 SIA Awards Dinner
Nov. 19 | San Jose, CA

2026 MRS Fall Meeting & Exhibit
Nov. 29–Dec. 4 | Boston, MA

CadenceCONNECT: Conformal AI Technology Day
Dec. 3 | San Jose, CA

SEMIEXPO Vietnam 2026
Dec. 3–4 | Ho Chi Minh City, Vietnam

ChipAgents Essentials Training: Powered by IC-star
Dec. 4 | Santa Clara, CA

SEMICON Japan 2026
Dec. 9–11 | Tokyo, Japan

IEEE Semiconductor Interface Specialists Conference
Dec. 9–12 | San Diego, CA

2026 GSA Awards Celebration
Dec. 10 | Santa Clara, CA

IEDM 2026: International Electron Devices Meeting
Dec. 12–16 | San Francisco, CA

CES 2027
Jan. 6–9 | Las Vegas, NV