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Oct 15Thu
  1. Semiconductor Engineering Chips and Packaging46

    Characterization of HBM Power Consumption (ETH Zurich, NYU)

    Researchers from ETH Zurich and NYU published a paper presenting the first comprehensive experimental characterization of power consumption on real HBM2 DRAM chips, with 13 new findings and 6 key conclusions. Read operations draw significantly more current than other operations, and flipping all bank group bus signals increases power by 29.4% over holding them constant. Based on this, the team constructed access patterns that on average consume 23.6% more power than the JEDEC-specified maximum power measurement loop across 36 tested HBM2 chips.

Oct 13Tue
  1. Semiconductor Engineering Chips and Packaging29

    Chip Industry Technical Paper Roundup: Oct. 13

    Semiconductor Engineering collects multiple recent chip technology papers, covering spatially deterministic nucleation of 2D semiconductors from KAIST and other institutions, the Hyper-NA EUV lithography system with a numerical aperture of at least 0.75 from Zeiss SMT and ASML, and BARE-AI from the University of Florida and others, which uses built-in performance monitors to defend against bit-flip attacks in AI hardware.

Oct 7Wed
  2. Semiconductor Engineering Chips and Packaging33

    Programmable Memory Controller Eases Adoption of New DRAM Techniques (ETH Zürich, CISPA, NYU)

    Researchers from ETH Zürich, CISPA, and NYU have published a paper proposing the Terracotta framework, which simplifies deploying new DRAM technologies through a flexible DRAM interface and a programmable memory controller. The framework includes two components: a custom command extension allowing DRAM vendors to define new commands within a single standardized interface, and a programmable memory controller that system designers can program after tape-out to support new DRAM technologies. The paper is available on arXiv (number 2610.06475).

Oct 6Tue
  1. Semiconductor Engineering Chips and Packaging22

    Chip Industry Technical Paper Roundup: Oct. 6

    Semiconductor Engineering collects several new chip technical papers: oxygen-doped WSe2 monolayer ballistic p-type transistors achieve low contact resistance and high current density; UC Santa Cruz explores the design space of backside clock mesh networks for 2nm GAAFET backside power delivery technology.