Chip Industry Technical Paper Roundup: Oct. 6
Chip Industry Technical Paper Roundup: Oct. 6
Semiconductor Engineering collects several new chip technical papers: oxygen-doped WSe2 monolayer ballistic p-type transistors achieve low contact resistance and high current density; UC Santa Cruz explores the design space of backside clock mesh networks for 2nm GAAFET backside power delivery technology.
Low-contact-resistance WSe₂ transistors; backside clock meshes for 2nm GAAFETs; row-parallel processing in DRAM; HBF for high-throughput LLM serving; formal security analysis of CAN XL; abstraction and validation from physical devices to RTL.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Low contact resistance and high current density in ballistic p-type transistors based on oxygen-doped WSe₂ monolayers | HUST, PolyU, UC Santa Barbara, National University of Singapore |
| Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology | UC Santa Cruz |
| RAPID: Row-Parallel Arithmetic Processing in DRAM | Syracuse University, FAU Erlangen-Nürnberg, TU Dresden |
| Characterizing High Bandwidth Flash for LLM Serving | UC Berkeley, FuriosaAI |
| A Formal Security Analysis of CAN XL | Georgia Tech, Qatar Computing Research Institute, Purdue University |
| From Physical Devices to RTL Models: Abstraction and Validation in Hardware Engineering | Infineon Technologies, TU Munich |
Find more semiconductor research papers here.
Linda Christensen
(all posts)
Linda Christensen is vice president of operations and a contributing writer at Semiconductor Engineering.
Source: Semiconductor Engineering Chips and Packaging · semiengineering.com