Chip Technology Paper Roundup: WSe2 Transistors, Backside Clock Grids, and More
Understand the story
This event is an ongoing roundup of chip industry technical papers. On October 6, 2026, Semiconductor Engineering published a new edition of its curated selection of chip and packaging papers, including several new studies: one on oxygen-doped WSe₂ monolayer ballistic p-type transistors, achieving low contact resistance and high current density; another on backside clock grid design space from UC Santa Cruz exploring backside power delivery for 2nm GAAFET; it also covers HBF LLM serving content. The event remains at the paper roundup update stage, with no further progress reported.
AI overview of reporting · Updated 11 days ago
Reporting timeline
Explore different aspects of the story through its reporting.
- Semiconductor Engineering Chips and PackagingChip Industry Technical Paper Roundup: Oct. 6
Semiconductor Engineering collects several new chip technical papers: oxygen-doped WSe2 monolayer ballistic p-type transistors achieve low contact resistance and high current density; UC Santa Cruz explores the design space of backside clock mesh networks for 2nm GAAFET backside power delivery technology.