Semiconductor Engineering 博客综述（11 月 4 日）：从 Chiplet、机架级设计到 AI 数据中心

Chiplets for physical AI; rack-level considerations; verification complexity; sparse matrix workloads; AI data centers.

Cadence’s Mick Posner introduces a physical AI sub-project workstream to extend the OCP’s Foundation Chiplet System Architecture’s data center, cloud, and server-centric baseline with the specification requirements to satisfy real-time, safety-critical physical systems, while retaining everything FCSA already defines.

Synopsys’ Charlie Matar considers how design focus is shifting from the server to the rack, with silicon behavior shaping rack-level power and cooling requirements, while rack constraints influence decisions inside chips and packages.

Siemens’ Harry Foster warns that while verification complexity has been managed by dividing large problems into smaller pieces, new challenges are emerging as the number and diversity of interactions influencing correct SoC behavior grows.

Arm’s Zenon (Zhilong) Xiu examines how quarter-tile and structured sparsity outer product instructions make the SME2 programming model better suited to small, dense, quantized, and sparse matrix workloads in modern AI software.

Keysight’s Linas Dauksa digs into AI data center infrastructure, including key components, energy demands and power density challenges, the array of liquid cooling technologies available, and what differentiates hyperscale facilities.

SEMI’s Sungho Yoon considers factors related to a forecasted increase in wafer shipments, including rising process material sales and a high number of new and upcoming production lines.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Technology editor Brian Bailey poses the age-old question for anyone involved in the verification of semiconductor systems: in the age of AI, who verifies the verifier?

Axiomise’s Vidya Chandran Darbari and Ashish Darbari dig into what biological reasoning can teach us about verifying silicon systems.

Keysight’s Chris Mueth explains why applying the appropriate level of simulation and abstraction at each stage of the design process is needed for effective thermal analysis.

Siemens EDA’s Emma-Jane Crozier explores how self-verifying agents validate their decisions and why physics-based engines are the authority on correctness.

Arteris’ Leon Brown looks at which products may fall within the EU Cyber Resilience Act’s scope and what information may need to be provided to customers.

Movellus’ Aakash Jani and Siemens’ Henrique Mendes and Robert Wilcox separate false failures caused by voltage droop from real structural defects.

ChipAgents’ Zackary Glazewski demonstrates how to deal with difficult bugs while intelligently deciding what to investigate, what to rerun, and where to spend compute.

Vinci’s Hardik Kabaria examines why physics-based analysis becomes more consequential as chips, packages, boards, and systems are designed together.

Cadence’s Reela Samuel breaks down how to orchestrate multi-step engineering workflows to reduce repetitive effort and explore more design options.

Synopsys’ Anand Thiruvengadam outlines how autonomous engineering agents pursue an objective requiring hundreds or thousands of reasoning steps while maintaining context, evaluating results, and adapting along the way.

Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.