Semiconductor Engineering 博客回顾（10 月 28 日）：STCO 异构设计、物理 AI 交互与 AI 生成设计签核

STCO for heterogeneous design; physical AI interactions; signing off AI-generated designs; workload profile analysis.

The eBeam Initiative’s Jan Willis reports insights from an expert panel discussion on large-format masks, equipment investment, high-NA EUV, and curvilinear masks.

Siemens’ Kevin Rinebold and Andras Vass-Varnai explore the shift toward chiplet-based and heterogeneous design and why system technology co-optimization and multiphysics analysis are becoming essential for addressing thermal, power, and integration bottlenecks.

Synopsys’ Sumit Vishwakarma argues that physical AI systems will require a new form of engineering that co-designs and validates the interaction of silicon, sensors, software, mechanics, and power using a holistic, physics-aware approach.

Cadence’s Reela Samuel finds that as AI is increasingly capable of generating RTL, proposing ECOs, modifying constraints, or creating verification properties, the question of whether the resulting design still meets its requirements has become more important than ever.

Arm’s Alan Chen explores how to enable source-less microarchitectural analysis using an evidence-first harness engineering approach that combines indexed workload data, bounded LLM analysis, and simulation evidence to improve optimization results.

Keysight’s Eric Yu explains why tensor parallelism is the first parallelism dimension that any scale-up fabric, whether it’s NVLink or Ethernet, must get right.

SEMI’s Paul Carey identified seven themes shaping the MEMS and sensors industry, with markets like robotics and medical bringing new requirements and opportunities for differentiation.

Plus, check out the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:

Synopsys’ Germain Fenger demonstrates why better models, richer metrology, explainable AI, and cross-industry collaboration must come together to extend semiconductor scaling.

Amkor’s Gerard John outlines why today’s high-performance processors are increasingly systems in their own right.

Lam Research’s Qingpeng Wang shows how a self-aligned CFET process sequence for SRAM and logic delivers higher performance through larger effective channel width and improved electrostatics at smaller nodes.

Intel Foundry’s Kaladhar Radhakrishnan, Nicolas Butzen, and Vishal Javvaji dig into how integrated voltage regulators reduce current density, provide higher regulation bandwidth, and reduce reliance on large decoupling capacitor networks.

Advantest’s Clemens Leichtle outlines new photonics test requirements, including fiber alignment, coupling efficiency, polarization management, and optical instrumentation.

Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.