突破 AI 与 HPC SoC 的内存瓶颈：GAA 节点下的嵌入式存储 IP
Breaking The Memory Bottleneck In AI And HPC SoCs
嵌入式存储而非计算，正成为 AI 与 HPC SoC 的瓶颈，占芯片面积一半以上。Synopsys 白皮书分析了 GAA 器件与背面供电（BSPDN）如何改变嵌入式存储需求，并给出 Intel 18A 上 SRAM 和 Register File 测试芯片的实测结果：密度提升 5–10%，ISO-power 性能提升最高约 4%。
Opimizing embedded memory IP for RibbonFET and PowerVia.
Embedded memory, not compute, has become the limiting factor in AI and HPC SoCs, consuming more than half of total die area while constraining bandwidth, latency, and energy efficiency. As the industry transitions to gate-all-around (GAA) devices and backside power delivery network (BSPDN) technology, embedded memory architectures must evolve to keep pace.
This white paper examines how these shifts redefine embedded memory requirements and how Synopsys Embedded Memory IP addresses them through device-aware architectures, power-optimized designs, and highly configurable compilers. It also presents silicon results from SRAM and Register File test chips on the Intel 18A process node, including density improvements in the 5–10% range and ISO-power performance gains of up to approximately 4%.
Read the paper to discover how RibbonFET and PowerVia enable PPA improvements and reduce advanced-node integration risk.
What you’ll learn:
- Why embedded memory, not compute, is limiting AI and HPC SoC performance
- How GAA devices and BSPDN technology reshape advanced-node embedded memory
- The critical PPA, power-delivery, and configurability requirements for embedded memory IP
- How RibbonFET and PowerVia enable measurable PPA improvements
- What silicon-proven SRAM and Register File results show on Intel 18A
To read more, click here.
来源： Semiconductor Engineering 芯片与封装 · semiengineering.com