Intel Foundry 解析堆叠多芯片架构下扩展与供电的权衡

By Kaladhar Radhakrishnan, Nicolas Butzen, and Vishal Javvaji

The semiconductor industry has embraced multi-chip and stacked-die architectures as the primary path for continued performance scaling. As monolithic designs become more difficult and costly to advance, chiplets, advanced packaging, and 3D integration enable higher levels of performance, bandwidth, and functional integration for AI and high-performance computing (HPC) systems.

Yet the success of stacked-die, multi-chip architectures has exposed a growing power delivery challenge. As more compute resources are integrated into a package, there is a sharp uptick in current density and the number of independent voltage domains, placing unprecedented demands on shared power delivery resources.

To address these challenges, we discussed in our recent power delivery white paper how Intel Foundry is moving voltage regulation closer to the load. By enabling higher-voltage power distribution, integrated voltage regulators (IVRs) reduce current density in the package, provide higher regulation bandwidth, and reduce reliance on large decoupling capacitor networks. Intel Foundry’s portfolio spans package-integrated magnetic inductors, fully capacitive IVR chiplets, and advanced package integration technologies, providing multiple paths to improve power integrity, efficiency, and scalability.

System-level consequences of stacked-die architectures

Advanced packaging delivers significant gains in performance, bandwidth, and integration density. However, consistently distributing power through increasingly complex packaging and interconnect structures introduces new challenges in maintaining power integrity across the package.

One consequence is voltage droop. As AI workloads generate rapid swings in current demand, the power delivery network must respond instantly. When it cannot, voltage can briefly fall below target levels, potentially impacting performance. To maintain reliability, designers often add voltage guard bands and operating margins. While effective, these safeguards can limit silicon from reaching its optimal efficiency and performance.

Multi-chip and stacked-die architectures also intensify the tradeoff between signal density and power delivery. As more compute tiles, memory interfaces, and die-to-die links are added, routing congestion increases, creating additional resistance, tighter voltage margins, and growing power delivery constraints.

Moving power delivery closer to the load

As current density continues to increase, the industry is moving toward architectures that bring voltage conversion closer to the point of consumption, reducing power delivery losses while improving responsiveness to rapidly changing workloads. Intel Foundry is advancing several complementary technologies designed around this principle.

FIVR with CoaxMIL: Intel was an early pioneer of fully integrated voltage regulators (FIVRs), which moves the last voltage conversion stage onto the processor. By shortening the distance between the regulator and the load, FIVR helps reduce distribution losses and improve transient response.

To support rising current densities, Intel developed CoaxMIL, a magnetic inductor technology that delivers significantly higher current density than earlier approaches while requiring less area (see Figure 1). For customers building next-generation AI and HPC devices, this translates into improved power conversion efficiency, faster response to workload changes, and more efficient use of valuable package real estate. The result is greater performance potential without proportional increases in power delivery complexity.

Fig. 1: CoaxMIL magnetic inductor technology.

C2VR: Intel Foundry’s continuous capacitive voltage regulator (C2VR) takes voltage conversion in a different direction. Rather than relying on traditional inductors, C2VR uses high-density capacitor technology to achieve efficient voltage conversion in an extremely compact form factor.

Because capacitors are integrated directly onto the voltage regulator chiplet, C2VR can deliver both high efficiency and exceptionally high current density. It can also respond rapidly to sudden current demands, helping minimize voltage droop during the bursty workload transitions common in AI accelerators. For customers, the benefit is improved power integrity, tighter voltage control, and a scalable solution capable of supporting future multi-kiloamp workloads.

IVR chiplet architectures: These dedicated power management chiplets allow voltage conversion to be positioned closer to the compute die than traditional motherboard-based regulators. The primary advantage of IVR chiplet architectures is flexibility. Architects can position voltage regulation where it delivers the greatest benefit, whether on the landside, embedded within package layers, or beneath compute dies. This flexibility allows architects to optimize power delivery for specific applications while reducing distribution losses and improving overall efficiency. In advanced stacked-die systems, these architectures also open the door to vertical power delivery schemes that reduce distribution distance and improve power integrity.

The future of power delivery

As AI systems continue their rapid evolution, power delivery is becoming as critical to performance scaling as transistor and packaging innovation. The next generation of data center architectures will require a portfolio of solutions that move power conversion closer to the load, improve efficiency at extreme current densities, and maintain stable operation under increasingly dynamic workloads. Intel Foundry technologies are important building blocks, helping ensure that future compute platforms can continue scaling performance without being constrained by the power delivery network.

This blog is the second in a two-part series on power delivery innovation. Part 1 explores how data center energy trends are affecting chip power delivery.

Nicolas Butzen is a principal engineer at Intel.

Vishal Javvaji is a process integration manager at Intel Foundry.