UCSC 论文探讨背面时钟网格如何降低 2nm 纳米片工艺的偏差与功耗

Backside Clock Meshes Cut Skew and Power in 2nm Nanosheets (UCSC)

AI 导读

加州大学圣塔克鲁兹分校研究团队发布了首个背面时钟网格的设计空间探索，基于 2nm GAAFET BSPDN 工艺在 OpenROAD 和 GT2N 上实现。背面供电网络在晶圆背面提供厚、低电阻金属层，可降低时钟偏差与功耗；由于触发器仍在正面，所有连接需经硅通孔。论文于 2026 年 10 月发布在 arXiv（arXiv:2610.02401）。

正文 · 原文

Researchers at the University of California, Santa Cruz published a technical paper titled “Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology.”

Abstract Excerpt: “Clock meshes are used in high-performance VLSI designs to minimize skew and tolerate on-chip variation, but they spend scarce routing resources on premium metal layers. Backside power delivery creates a new option: it adds thick, low-resistance metal layers on the back of the wafer, and the power grid does not consume all of them. Flip-flops remain on the frontside; a backside mesh therefore cannot drive them directly, and every connection passes through a through-silicon via. We present the first design-space exploration of backside clock meshes, implemented in OpenROAD on GT2N, a 2 nm nanosheet technology.”

Find the technical paper here. October 2026.

Ali, Wajid, Muhammad Hadir Khan, Dalton Gaddy, and Matthew Guthaus. “Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology.” arXiv preprint arXiv:2610.02401 (October 2026). https://doi.org/10.48550/arXiv.2610.02401

The post Backside Clock Meshes Cut Skew and Power in 2nm Nanosheets (UCSC) appeared first on Semiconductor Engineering.