为什么人人都在谈混合键合，谁在这场竞赛中——TrendForce 解析 3D 封装格局

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From OCP APAC and Hot Chips in August through SEMICON Taiwan in September, advanced packaging has continued to gain momentum across the semiconductor industry. Why does advanced packaging matter? Transistor scaling is approaching its physical limits, so to maximize efficiency within a single package, the industry is moving rapidly toward chiplet stacking and heterogeneous integration.

In our previous article, we looked at the advanced packaging market as a whole. We also compared TSMC’s CoWoS and Intel’s EMIB, the two leading 2.5D platforms, on specifications and key customers. This article turns to 3D packaging, and to hybrid bonding in particular.

Types of advanced packaging: 2.5D, 3D, and 3.5D

Quick recap: 2.5D packaging uses an interposer with extremely high routing density, enabling faster signal transmission and lower power consumption between dies. Examples include TSMC’s CoWoS and Intel’s EMIB (which embeds a small silicon bridge in the substrate instead of using a full interposer).

3D packaging stacks dies vertically to shorten the communication distance between them, as in TSMC’s SoIC and Intel’s Foveros Direct 3D. Both enable an integrated “3.5D” solution that combines 2.5D and 3D packaging in a single architecture. Multiple chips are vertically stacked into a single composite IC, which is then integrated with HBM or other peripheral ICs through 2.5D packaging.

According to TSMC, SoIC with 3D interconnect offers 56x interconnect density and 5x power efficiency over CoWoS with 2.5D interconnect. TSMC commenced mass production of SoIC with a 6µm bond pitch in 2025, and the company expects to further scale SoIC to a 4.5µm pitch by 2029.

On the Intel side, Foveros Direct reached volume production in 1H26 with the Clearwater Forest Xeon 6+ at a 9µm bond pitch. A second generation targeting 3µm is on the roadmap.

Related report: 2Q26 Revenue Ranking among Top 10 Global Foundries

Not only does 3D IC enable logic-on-logic stacking, but it also opens up possibilities for memory-on-logic or logic-on-memory stacking. For example, 3D DRAM architecture places DRAM directly on top of the logic die.

Architecture of 3D DRAM. Source: SK hynix

Building upon the foundation of 3D ICs, the industry is also striving to miniaturize optical components, integrate them into silicon chips, and co-package them with EICs to form optical engines, a technology known as CPO. This paradigm further elevates the complexity of 3D packaging. One example is TSMC’s COUPE, which utilizes hybrid bonding to integrate EICs and PICs. COUPE has been applied in NVIDIA’s Spectrum-X Photonics and Tomahawk 6-Davisson.

ASE has introduced its SiPh Optical Engine, which uses micro-bump technology to vertically bond the EIC and PIC. Intel has launched the OCI (Optical Compute Interconnect) chip that integrates the laser into the PIC, while GlobalFoundries has unveiled the SCALE (Silicon Photonics Co-packaged Advanced Light Engine) platform, which combines FAU and Fiber Array.

Behind the paywall, we explore:

Micro-bump + TCB vs. hybrid bonding, and where each is adopted
Alignment accuracy across major hybrid bonder suppliers, and who is closing the gap
Three challenges beyond bonding, and how the industry is responding
Two indicators to track: TSMC’s SoIC capacity plan and Besi’s order intake

Related report: 2026 3D IC Outlook: SoIC Ramp-Up, Rise of STCO