SEMICON West 2026：芯片扩展正从晶体管走向系统级整合

Key Takeaways:

• The semiconductor industry reached $1 trillion years early, but keeping pace with demand now depends on systems integration as much as transistor scaling.
• Packaging, photonics, power, and test are converging into one optimization problem, which means improving any one of them can move the bottleneck somewhere else.
• AI is shifting from the workload the industry serves to a tool it uses, and the open question is how much engineering and manufacturing authority it will be given.

When SEMICON West gathered in San Francisco in 2023, the semiconductor industry was forecasting a path to $1 trillion in annual revenue by 2030. Three years later, the industry has already blown past that number. SEMICON West 2026 returned to San Francisco with a sold-out exhibit floor, more than 30,000 attendees, and an industry confronting a different question: How does it keep up with the growth it once aimed for?

SEMI’s own projections show how steep that curve has become. In his opening keynote, SEMI President and CEO Ajit Manocha forecast a market of more than $2 trillion by 2030, and potentially $3 trillion by 2035. At the SEMI Market Symposium, the association projected 300mm fab equipment spending of $149 billion this year, rising to $227 billion by 2029, with construction beginning on 20 new 300mm fabs or production lines in 2026 alone.

AI infrastructure is driving much of that growth, but electrification, autonomous vehicles, robotics, and industrial automation are adding semiconductor content, as well. What makes the current expansion unusual is the growing complexity of the systems those chips will enable, not the almost insatiable demand for chips.

“We’ve started talking about how to re-engineer engineering because you need to co-design and optimize across multiple intersections,” said Sassine Ghazi, president and CEO of Synopsys. “That’s at the physics level, material, process technology, architecture, design, along with the software and the model itself, because the model itself is what’s defining the workload, and how do you optimize along that stack?”

Across presentations, panels, and discussions on the show floor, several issues kept converging around that problem. Advanced packaging is becoming part of system architecture. Photonics is moving closer to compute, while bringing new manufacturing and test challenges with it. Test, inspection and metrology have to follow more complicated assemblies and manufacturing histories. And AI is moving from something the industry builds to something it uses to design and manufacture. None of these technologies is new, but each is becoming harder to optimize independently, and that may be the clearest indication of what the industry will be working on in the coming years.

Scaling becomes a system-level challenge
The shift was apparent in conversations ranging from transistor scaling and HBM to advanced packaging, optical interconnects, and cooling, where improving any one of those can move a bottleneck elsewhere. More compute increases pressure on memory bandwidth and power delivery. Moving memory closer reduces data movement but concentrates heat. Disaggregating a large die can improve yield and allow functions to use different process nodes, but it creates more interfaces that have to be connected, powered, cooled, and tested.

“Packaging is no longer simply the place where semiconductor innovation ends,” said Lalitha Immaneni, vice president of semiconductor R&D at Intel Foundry. “Increasingly, it’s the place where system innovation begins.”

That makes memory, data movement, power delivery, and thermal management part of the architecture rather than downstream considerations.

“The challenge is not to co-optimize one component,” Immaneni said. “It is to co-optimize across the system from end to end between silicon, packaging, and platform.”

Nitin Deshpande, Marvell’s vice president of advanced packaging, made a similar point during imec’s pre-show ITF USA program. “The package is really becoming a system where the compute, the memory, the interconnects, the power, the cooling, all of these things come together.”

Making those pieces work together is only part of the challenge. Larger, more heterogeneous packages still have to become high-volume products with acceptable yield, reliability, and cost.

“We can have very cool concepts, but if we cannot scale these into high volumes, if we cannot have a high-yielding, reliable process with a supply chain that can provide the parts in time, everything that we do cannot be converted into a business,” Deshpande said.

Patrick Vandenameele, CEO of imec, noted that AI infrastructure can keep growing by adding accelerators and racks, but adding hardware isn’t scaling in the traditional semiconductor sense. “These data centers are true engineering marvels,” he said. “But at the same time, this is not what we semiconductor people call scaling. It looks a little bit more like multiplication.”

That distinction helps explain why so many separate topics at SEMICON West kept leading back to the same place. The industry isn’t abandoning transistor scaling. It’s adding another level above it, where performance depends on how effectively different technologies can be combined into a functional system.

Fig. 2: Redefining a system. Source: SEMI

AI moves from assistant to operator
AI was nearly impossible to avoid at SEMICON West, but the conversation is shifting. Machine learning has been part of design, process control, and defect classification for years, and generative AI added natural-language access to complicated tools and data. Agentic AI goes further, allowing engineers to hand an agent an objective and let it invoke other tools, models, or agents to reach it.

“We started from an assistant copilot to generative capability to now what we’re describing as long-horizon autonomous agents, where instead of giving a prompt, you give an outcome,” said Synopsys’ Ghazi.

The appeal of agentic AI becomes clearer when looking at the size of the spaces engineers are being asked to optimize. “The space that we’re optimizing in has exploded,” said David Fried, chief AI officer and corporate vice president of Semiverse Solutions at Lam Research. “We’ve now gotten to a place where the parameter set is intractable.”

A current Lam etcher, for example, can have a potential recipe space on the order of 10²³ possibilities, which is well beyond what any engineer can explore manually. “That’s really where AI is coming to the rescue,” Fried said. “It’s the ability to get through massive multi-parameter dimensional spaces, massive sets of intertwined sensitivities between a much larger parameter space, and a much larger spec space.”

Acting on what AI finds is where the discussion gets more complicated. Flagging an unusual process signature is different from letting an AI system alter a recipe, and predicting equipment degradation is different from stopping production. Ghazi said Synopsys already has engagements where autonomous agents can take a customer specification through verified RTL. This is work that traditionally required multiple engineers and months. Human judgment is still needed to define the architecture and sign off before manufacturing, but the boundary is moving.

On the manufacturing side, that raises questions likely to become more prominent over the next year. What decisions can an agent make without approval? How much of its constraint comes from physics-based models rather than statistical inference? What evidence is required before an autonomous decision can affect production?

The question coming out of SEMICON West isn’t whether AI will be used to design and manufacture semiconductors. That’s already happening. The new question is how much authority engineers are prepared to give it.

Fig. 3: What comes next is an evolving topic of great interest to a lot of people. Source: SEMI

Packaging has to become manufacturable
Advanced packaging showed up almost everywhere, but the emphasis has moved beyond proving that heterogeneous integration works. The harder problem is doing it repeatedly, economically, and at volume while protecting the value accumulated during assembly. That is changing the meaning of “known good.”

Known-good die has been an objective for years, because attaching a bad die to a good package wastes everything around it. As substrates, bridges, and intermediate assemblies grow more complicated and expensive, the same logic is moving outward.

“Even though the bridge is a passive component with just metal lines, we sort it,” said Ravi Mahajan, Intel fellow and director of substrate and advanced packaging pathfinding at Intel Foundry. “We make sure we have known-good bridges going into a package, and what comes out should be a known-good package.”

Mahajan was careful to treat “known good” as an aspiration rather than an absolute.

“You bring into your assembly process a known-good substrate, and the word ‘known-good’ has to be understood,” Mahajan said. “It’s not always known-good, but you know as much of this as you can. And to do that, you put in the right kind of features to test so that you have as much coverage as possible.”

ASE is approaching the problem in much the same way. In some fan-out flows, the interconnect structure can be fully tested before any active silicon is attached.

“The known-good methodology is what we’re striving for,” said Yin Chang, executive vice president of ASE. “Everything we do, every layer, we have the ability to confirm that it is good before we put on the most expensive part.”

Some silicon and HBM combinations can represent as much as $30,000 in value, and ASE uses AOI and X-ray extensively, with AI helping distinguish subtle differences across assemblies that can contain as many as half a million joints.

“The goal for our industry is trying to take out as much unknown as we can in the overall processes,” Chang said. “It is too expensive already today. We just can’t scrap anything.”

Assembly complicates that goal. Bonding creates interfaces that didn’t exist when the individual components were inspected, and heat, pressure, and materials interactions can alter the state of the assembly, so some defects can’t be detected until another process step has occurred. The objective progressively becomes how to reduce uncertainty as value is added, and the sampling calculation shifts from how much inspection maintains yield to how much uncertainty a manufacturer can afford to carry into the next step.

Test follows the system
That same pressure is reshaping test, particularly as photonics enters the package. Digital manufacturing test compares a response with an expected result, but optical devices can produce a range of acceptable responses that still have to be correlated with possible defects. Co-packaged optics adds a physical problem, as well.

“What our customers are demanding from OSATs is to be able to do optical tests on the top side and electrical tests on the bottom side, and expect efficiencies,” said Vineet Pancholi, senior director, manufacturing test technologist at Amkor. “Even if the ASPs are that high, they are still looking for manufacturing tests to be way more efficient.”

“The mechanical structure is different,” Pancholi said. “The package, physical x,y,z, weight of the package, the density of the package — that’s all changing. All of it is changing.” Asked whether those changes were increasing test-cell time, the number of insertions, or both, he added, “It is impacting all of those things.”

Knowing where a problem occurred also depends increasingly on retaining information from earlier process steps.

“Even if you don’t know exactly what layer it is, you know where in the process it was not,” said Reiner Fenske, CEO of Microtronic. “And that’s really big.”

Microtronic is approaching inspection partly as a historical record, retaining wafer images that can be compared across process steps when a defect appears later. That becomes increasingly valuable as additional layers make earlier defects difficult or impossible to see.

“The information that we gather is so valuable that throughput is a secondary issue, but having the history, that’s key,” Fenske said. “So six months from now, you can actually grab exactly what happened before.”

Determining whether something is good increasingly requires context. Wafer test results, inspection data, assembly history and earlier insertions can be fed forward to alter later testing or fed backward to identify process drift. At the same time, following a die from its original wafer coordinates through reconstituted wafers, panels and multi-die assemblies makes traceability much harder.

Test is becoming less a final pass/fail gate than a continuous evidence trail, and that brings it into the AI discussion as well. AI can find patterns across that history, but only if the data can be tied to the right device, process step, and physical context.

Photonics faces manufacturing challenges
The motivation for photonics is well established. Electrical interconnects struggle with power and signal integrity as bandwidth and distance rise, pushing optics from pluggable modules toward near-package and co-packaged designs. The closer optics gets to compute, however, the more the problem moves into semiconductor manufacturing.

“For precision bonding, it needs to not only control in all six degrees of freedom,” said Huan Ma, senior technologist at Intel Foundry. “It also needs to deliver throughput at a semiconductor manufacturing scale with automation and standardized material handling.”

The same requirement extends to materials, which have to preserve alignment through assembly, reflow and reliability stresses, and to metrology.

“For metrology and inspection, how do we measure the variables that actually predict optical yield?” Ma said. “We need to measure the geometry, the angles, the positions of optical features, and what really matters to the insertion loss and to the coupling efficiency. Co-packaged optics will not scale just because the optics work. It will only scale when we industrialize the optics through advanced packaging.”

The same issues surfaced across the show floor. EV Group pointed to the metrology and throughput burden of measuring multiple alignment points across hundreds of dies in die-to-wafer integration. Lam Research discussed waveguide fabrication, new modulator materials, and fiber coupling. Advantest described high-volume test as one of the remaining bottlenecks, with electro-optical probing and optical connectors adding requirements that don’t exist in electrical test.

Assembly complicates known-good here, too, because alignment, bonding, thermal processing and fiber attachment can alter an optical path that met specification before integration.

“Coming through the door, you have an understanding of what is known good on the PIC and the EIC,” Intel’s Mahajan said. “The biggest question is how do you ensure you have alignment? These processes in photonics are not recoverable and not reworkable, so we have spent a lot of time figuring out the yield limiters in assembly.”

Mahajan doesn’t see an intrinsic barrier, pointing to fiber attachment as a step considered particularly difficult less than a decade ago, but which has improved substantially through repeated process learning.

“I cannot think of any intrinsic showstoppers in any of these processes,” he said. “It’s now a matter of practice to do it right.”

The question surrounding co-packaged optics is becoming less about whether the technology can work and more about how quickly it can be aligned, inspected, tested, and manufactured at semiconductor volumes.

Engineering boundaries are blurring
What stood out at SEMICON West was how often discussions in one area crossed into another. A package decision becomes a thermal decision. Memory placement becomes a power decision. Photonics becomes a packaging and test problem, inspection becomes a data problem, and manufacturing data becomes an AI problem. The old engineering boundaries still exist organizationally, but they increasingly don’t describe the physical system.

In her keynote, Intel’s Immaneni described the response as moving beyond design-technology co-optimization toward system-technology co-optimization, where silicon, packaging, and platform are considered together.

“A beautiful technology can be a good choice, but if I cannot manufacture it repeatedly, quickly, and with high quality, then it is not a customer technology,” she said.

Digital twins fit into the same transition, but their value depends on connecting electrical, thermal, mechanical, and manufacturing models closely enough that a decision in one domain can be evaluated against its consequences in the others. During his discussion with Semiconductor Engineering Editor-in-Chief Ed Sperling, Synopsys’ Ghazi added the workload to that list, since model behavior can drive power and thermal conditions in the hardware underneath it. As AI expands into robots, vehicles and other physical systems, sensors, safety requirements and real-time constraints compound the problem further.

Conclusion: Five months to Phoenix
SEMICON West won’t have a full year to see how those conversations develop. This was the show’s last scheduled run in San Francisco. SEMI has signed a three-year agreement with Phoenix, and the next event moves to the Phoenix Convention Center March 30 through April 1, 2027, beginning a new spring schedule. That leaves about five months between shows, and some useful markers should be visible by then.

Fig. 4: View from the show floor. Source: SEMI

Agentic AI will be judged by which engineering and manufacturing decisions companies are willing to let agents make, and the constraints they apply. Heterogeneous integration will put more pressure on inspection, metrology, and test to establish confidence before more value is committed to assembly. Co-packaged optics will have to move from demonstrations toward repeatable manufacturing. Alongside those, high-NA EUV is moving toward production, power delivery is moving deeper into packages, and materials suppliers are being asked to understand interface and process interactions that aren’t part of traditional specifications.

Three years ago, SEMICON West was talking about how the industry could reach $1 trillion by 2030. Having reached that milestone years early, the conversation has changed. The challenge is no longer just increasing density or manufacturing more chips. It’s building increasingly complex semiconductor systems fast enough, reliably enough, and economically enough to keep pace.

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