Chip Industry Technical Paper Roundup: Oct. 20
Chip Industry Technical Paper Roundup: Oct. 20
Semiconductor Engineering has published several new chip technology papers: Argonne National Laboratory and the University of Illinois Urbana-Champaign research agentic AI heterogeneous system design across chip, scale-up and scale-out domains; Sandia National Laboratories uses first-principles simulations to reveal new GAAFET leakage paths.
HBM power consumption; GAAFET leakage pathways; agentic AI for heterogeneous system design; nanoelectromechanical gain-cell eDRAM; AI-accelerated 3D-IC thermal modeling; agentic AI for RTL verification and debugging; thermal side-channel attacks in autonomous vehicles.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains | Argonne National Laboratory, University of Illinois Urbana-Champaign |
| Revealing New Leakage Paths in GAAFETs using Predictive First-Principles Simulations | Sandia National Laboratories, Luxembourg Institute of Science and Technology |
| Nanoelectromechanically Gated Gain Cell eDRAM | UC Berkeley, Samsung Electronics, Intel |
| A Composable AI-Accelerated Iterative Solver for 3D-IC Thermal Modeling | Cadence Design Systems, University of Notre Dame |
| Understanding the Power Consumption of Modern High Bandwidth Memory: Experimental Analysis and Modeling Using Real HBM2 DRAM Chips | ETH Zürich, New York University |
| Back to the Future: Rethinking EDA Infrastructure for Agentic Systems in Chip Design Verification | Columbia University, Google DeepMind, Google |
| Can Autonomous Vehicles Keep Their Cool? A Survey of Thermal Side-Channel and Perception Attacks | Missouri University of Science and Technology |
Find more semiconductor research papers here.
Linda Christensen
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Linda Christensen is vice president of operations and a contributing writer at Semiconductor Engineering.
Source: Semiconductor Engineering Chips and Packaging · semiengineering.com