Accelerating Manufacturing-Aware Simulations For Photonic Integrated Circuits With FTCO And Digital Twins
Accelerating Manufacturing-Aware Simulations For Photonic Integrated Circuits With FTCO And Digital Twins
An FTCO workflow for photonic integrated circuits chains GDS layout import, 3D process simulation, GPU-accelerated FDTD, DOE and AI surrogate modeling, so that simulation results including manufacturing variation match experimental data.
Fab workflow connects GDS layout import, 3D process simulation, GPU-accelerated FDTD, design of experiments, with AI-based surrogate modeling.
Photonic integrated circuit (PIC) performance is increasingly bounded by fabrication realities such as sidewall angle, critical-dimension bias, thickness variation, and line-edge roughness, which idealized, as-drawn FDTD simulations fail to capture. Here, we show a Fab Technology Co-Optimization (FTCO) workflow that connects GDS layout import, three-dimensional process simulation, GPU-accelerated FDTD, design of experiments (DOE), with AI-based surrogate modeling. We show that when manufacturing variations are included in the modeling that the simulation results align well with experimentally reported results. A directional-coupler DOE with 25 unique combinations of 4 different process variations requiring a 65-million-cell 3D FDTD model and completes in under 10 hours on a single NVIDIA A100-equipped workstation is showcased. The generated digital twin provides intuitive and real-time access to the process-to-performance relationship for non-simulation experts: A game-changer in the industry.
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Source: Semiconductor Engineering Chips and Packaging · semiengineering.com