Silvaco Shows AI Surrogate Models Accelerating Manufacturing-Aware PIC Simulation
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Silvaco demonstrated its FTCO workflow for manufacturing-aware simulation of photonic integrated circuits (PICs). The workflow chains together GDS layout import, 3D process simulation, GPU-accelerated FDTD, DOE (design of experiments), and AI surrogate modeling to incorporate the effects of manufacturing variation into designs. According to a Semiconductor Engineering report on October 21, 2026, with this simulation flow incorporating manufacturing variation, simulation results matched experimental data, demonstrating the acceleration achieved by combining AI surrogate modeling with digital twin methods in manufacturing-aware PIC simulation. The main factual source for this event is that report, and there is no information on further stage developments yet.
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- Semiconductor Engineering Chips and PackagingAccelerating Manufacturing-Aware Simulations For Photonic Integrated Circuits With FTCO And Digital Twins
An FTCO workflow for photonic integrated circuits chains GDS layout import, 3D process simulation, GPU-accelerated FDTD, DOE and AI surrogate modeling, so that simulation results including manufacturing variation match experimental data.
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