Using SEMulator3D digital twin modeling, Lam Research validated a self-aligned complementary field-effect transistor (SA-CFET) architecture that could extend CMOS scaling beyond the 10-angstrom node.
Lam Research has opened its largest US warehouse in Livermore, California—a 470,000-square-foot logistics and supply chain hub built to support semiconductor supply chain pressures driven by AI technology demand. A 40,000-square-foot automated storage and retrieval system with 15 robots cuts parts retrieval time from 6 minutes to under 30 seconds, 12 times faster than the existing system. The center is expected to support more than 200 jobs by 2027.
AI's demand for larger, more complex chip packaging is pushing the industry to explore panel-level packaging (PLP): replacing round wafers with rectangular panels to improve area utilization and scalability beyond traditional wafer-level packaging size limits. Lam Research is advancing the technology toward production readiness through tool innovation and infrastructure investments, including the Salzburg Panel Center of Excellence. The technology still faces challenges in uniformity control, yield management, and industry standards.
Lam Research has broken ground on a new laboratory expansion at its R&D center in Tualatin, Oregon. Once complete, the facility will add 120,000 square feet, expanding cleanroom space by more than 50%, with operation expected in 2028.
Lam Research used SEMulator3D® integrated stress modeling to predict stress non-uniformity across GAA stacked nanosheet channels before fabrication — nFET stress differences reach 400–800 MPa, while pFET stays below 200 MPa. DOE experiments show that channel thickness, fin width, and lateral etch jointly affect stress uniformity, with increasing the topmost channel thickness from 4 nm to 7 nm significantly reducing the stress difference.