半导体工程博客回顾（10月21日）：从服务器到机架、AMBA CXS、数字孪生等

From server to rack; AMBA CXS; digital twins; edge AI development loop; satellite power; global talent challenges.

Synopsys’ Neeraj Paliwal considers how AI workloads are shifting key design and optimization considerations from the server to the rack, with designs starting from the target workload and working backward to optimize for useful AI work per watt and dollar.

Cadence’s Ravi Vora demonstrates how AMBA CXS evolves a wide, credited link into a scalable shared transport for multi-protocol and multi-node traffic that enables controlled interleaving while preserving stream ordering, route identity, packet reconstruction, and required contiguity.

In a podcast, Siemens’ Conor Peick and Katherina Westrich chat about the adoption of digital twins in the semiconductor industry, ranging from chip design and verification to fab construction and automation.

Arm’s Christopher Seidl shows how to create a development loop for edge AI in which target information and evidence from real execution flow back into the next iteration.

Keysight’s Nancy Friedrich explores the trends driving rising requirements for satellite power generation and distribution and how lab-based power-emulation configurations can be leveraged to assess system performance in scenarios that affect the performance of satellite solar arrays and battery packs.

In a blog for SEMI, Stanton Chase’s Jan-Bart Smits compares semiconductor talent shortages across North America, EMEA, and Southeast Asia, warning that while causes differ by region, government subsidies alone cannot buy the expertise needed for desired buildouts.

Plus, check out the blogs featured in the latest Low Power-High Performance newsletter:

Rambus’ Paul Karazuba examines multiple interacting factors impacting PCIe retimer reach, including silicon design, controller intelligence, channel quality, and the transmission medium.

Siemens EDA’s Shehab Ashraf looks at short-resilient via insertion and its effect on reliability and performance.

Cadence’s Mayank Bhatnagar shows how open interfaces and interoperability let designers choose technologies based on system needs.

Arm’s Francisco Socal outlines extending chiplet connectivity across AXI and CHI with scalable protocol subsets, interoperability, and flexible transport support.

Ayar Labs’ Vladimir Stojanovic and Global Unichip’s Igor Elkanovich explain how optical engines can operate reliably alongside high-power AI processors in multi-chip packages.

Jesse Allen

(all posts)
Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.