ETH Zurich 与 NYU 首次对真实 HBM2 DRAM 芯片功耗进行实验表征
Characterization of HBM Power Consumption (ETH Zurich, NYU)
ETH Zurich 与 NYU 研究者发表论文，首次对真实 HBM2 DRAM 芯片功耗做全面实验表征，给出 13 项新发现和 6 条关键结论。其中读操作电流显著高于其他操作，翻转全部 bank group 总线信号会使功耗比保持恒定高 29.4%。团队据此构造的访问模式在 36 颗受测 HBM2 芯片上平均功耗比 JEDEC 规定的最高功耗测量环路高 23.6%。
Researchers at ETH Zürich and New York University published a technical paper titled “Understanding the Power Consumption of Modern High Bandwidth Memory: Experimental Analysis and Modeling Using Real HBM2 DRAM Chips.”
Abstract Excerpt:
“We perform the first comprehensive experimental characterization of power consumed by real HBM2 DRAM chips. Our extensive characterization yields 1) the empirical basis for developing new, accurate HBM power models or validating existing power models and 2) key insights into structural and data-pattern-dependent variation of power in HBM2 chips. Out of our 13 new findings and 6 key takeaway messages, we highlight: 1) a read operation consumes significantly higher current than any other operation and 2) the toggled data bus signals in a data transfer burst significantly affect current draw where toggling all HBM2-internal bank group bus signals causes 29.4% higher power consumption than keeping them constant. Leveraging our empirical insights into HBM2 power consumption, we engineer an access pattern that yields 23.6% higher power consumption on average across 36 tested HBM2 chips than the highest-power-consuming JEDEC-specified current measurement loop.”
Find the technical paper here. October 2026.
Olgun, Ataberk, Spiros Galanopoulos, Andreas Kosmas Kakolyris, İsmail Emir Yüksel, Haocong Luo, F. Nisa Bostancı, and Onur Mutlu. “Understanding the Power Consumption of Modern High Bandwidth Memory: Experimental Analysis and Modeling Using Real HBM2 DRAM Chips.” arXiv preprint arXiv:2610.14244 (October 2026). https://doi.org/10.48550/arXiv.2610.14244
来源：Semiconductor Engineering 芯片与封装 · semiengineering.com