Scaling CPO Testing Beyond A Single Die
Scaling CPO Testing Beyond A Single Die
Experts from Teradyne, Advantest, ISE Labs, and Keysight discussed paths for scaling CPO optical engine testing from single-site to multi-site. Fiber alignment is currently the main testing bottleneck; multi-site probe cards are expected to significantly ease this issue, and progress by companies such as Technoprobe in probe cards offers some hope.
Key Takeaways:
- Fiber alignment is the main bottleneck to optical engine testing, which would be alleviated significantly by multi-site probe cards.
- Optical connectors must be optimized for the best optical properties yet be mechanically robust to withstand assembly and use.
- Simultaneous loopback on both optical and electrical sides could simplify testing.
Experts At The Table: The industry is forging a path from single-site to multi-site testing while system architectures and connector types continue to evolve. Semiconductor Engineering sat down with Matt Griffin, senior product manager for optoelectronics test at Teradyne; Ira Leventhal, vice president of research and venture at Advantest America; Dave Armstrong, fellow at ISE Labs, a subsidiary of ASE Group; and Kazuo Yamaguchi, silicon photonics researcher and engineer at Keysight Technologies. What follows are excerpts of that conversation. To view part one, click here.

Fig. 1: (L-R): Teradyne’s Griffin; Keysight’s Yamaguchi; ISE Labs’ Armstrong; Advantest’s Leventhal.
SE: Is it true that you can only test one die at a time today?
Armstrong: I would hope some insertions will go away over time, but right now there are more things being added than being subtracted. It’s a hard one. In terms of testing one die, that depends on the die. If an 8 kW GPU is your main ASIC, and you have multiple connectors around multiple sides of the part from a tester resource standpoint, and the amount of power a tester can deliver and take out of the part, it’s pretty challenging to get beyond one die. But if you look down the NPO-versus-CPO path, NPO is typically a single connector device. You’re going to have to be able to go to multi-site to scale that to high volume. Insertions two and three are the fertile ground for multi-site. Those are longer more complex test insertions. PIC wafer testing tends to be single-site today. From my experience, there is some hope on the horizon to bring it up a little bit higher with some capabilities in the probe card area, notably from Technoprobe.
Griffin: I agree with Dave. Most production solutions today are single-site, and when you talk about the optical engine, the main bottleneck is fiber alignment. Many companies are working on multi-site solutions, and I hope they succeed and take off because that only helps the whole industry ramp faster. But we’ve got a little bit longer to go there.
SE: For these alignment ports, can you repeatedly test at that site?
Griffin: Ideally, you’re able to repeatedly test almost infinitely because you should never be contacting the device with the optical probe or the fiber array unit (FAU). When you’re bringing up a new test solution, you do sometimes crash FAUs on first systems. In reality, the bigger concern is contamination on the FAU, so cleaning is needed. On the connector side, at the module level or for optical engines with receptacles attached, the optical connector lifecycle is where we need more effort, because the device-side connector is designed to be attached once and, hopefully, never disconnected. And every new connector generation changes both the connector recipe and the automation recipe.
Leventhal: In a sense, this is nothing new. For instance, with BGAs, if you socket at the device too many times, then you start worrying about damaging the balls on the BGA. It’s a similar problem and the industry will gravitate toward connector designs that are more robust. Matt made a really important point about how your test side connector needs to be some sort of a hardened connector that doesn’t wear out easily after 20 to 50 insertions. It needs to last for tens of thousands or 100,000 insertions. So you’ve got to go to a hardened metal, and then you’ve got a hardened metal going against the receptacle on the device, which is not going to be that hardened metal. If you’re not careful, you could damage that connector sooner than the spec lifetime. So as the industry evolves to the winning connector designs, robustness on the device side is going to be a really important part of that.
SE: What are the challenges with making simultaneous electrical and optical connections?
Armstrong: It’s just a question of time.
Yamaguchi: Beyond DC and optical probing, the harder part of simultaneous electrical and optical connection is characterizing electro-optic devices in RF. Modulator and photodetector performance is ultimately validated through S-parameters, so you need optical and high-frequency RF contact at the same time. Probe cards can only fit a limited number of RF lines, and their bandwidth is also limited, while today’s devices are characterized beyond 200 GHz. At wafer and die insertions, simultaneous connection is really an RF probing challenge.
Leventhal: Warpage is going to create additional challenges on top of just trying to solve the problem in an ideal case. You need to be able to align in multiple axes. And the BGA has a crazy amount of pins that you have to make reliable contact with, so that problem is getting more challenging. Adding to that is being able to do the right level of alignment, either coming from the top or coming from the side. It’s significantly challenging. I agree with Dave, it’s a question of time in multiple senses. Each insertion takes time, although there are ways of minimizing that by integrating certain operations together. But also, it’s going to take time for all of this to mature to the point that it’s going to be easier to test at scale.
Griffin: At its core, there’s an optical and an electrical interface to the device at every insertion, and sometimes those interfaces are on the top side of the device, sometimes the bottom side, and sometimes both. And then when you talk about module level, they’re on two to four sides of the package across some number of optical engines. So if you look at optical alignment on its own, it’s not that big of a challenge. But when you start combining it with all the different, I’ll say, flavors of architecture that we’re seeing, and trying to design a scalable test system that can handle as many of those flavors as possible for your customers, that’s really where some of the fun challenges are.
Armstrong: I also chair the IPSR test roadmap for photonics, and in our latest report we highlight a test methodology for AC testing. AC testing, bit error rate testing, will be one of the bigger time sinks. If we had good DFT, we could just do loopback on the optical side and loopback on the electrical side at the same time. And technically, there’s no reason you couldn’t combine those two tests. But today, most people are saying, “Okay, I’ll do loopback on one side or the other side, and a bit error rate test of some nature on the other side, so that becomes a very expensive setup that doubles the effective test time. The more DFT and concurrent testing we do, the better off we’ll be in the long run.
Griffin: The automation challenge is still there, but I agree with Dave’s point. Most customers going to volume will have some sort of loopback capability — electrical, optical, or a combination — but it remains to be seen what wins out there.
SE: Which measurements dominate production test — optical power, insertion loss, or bit error rate?
Armstrong: In terms of test time, it seems like a lot of people are very concerned with insertion loss just because of how often it’s done, but I don’t think that should be number one. Eye quality would be number one, and high-quality receiver sensitivity would also be high on the list, and bit error rate.
Griffin: I agree. I’ll add wavelength sweeps for optical engines. Those can take a significant amount of time, depending on customer requirements.
Yamaguchi: I also agree, but we need to be mindful of correlating such performance with not only ‘known good die,’ but also ‘known good and reliable die.’ It’s the probability of surviving integration and service life, because defects that escape pre-assembly are largely integration-induced effects such as fiber/FAU coupling loss after attach, resonance drift versus laser tunability, thermal and packaging effects. In the end, overall transmitter and receiver performance are defined by standards, using metrics such as TDECQ (Transmitter and Dispersion Eye Closure Quaternary) and receiver sensitivity.
Leventhal: Going forward, the main issue is whether your data transmission is working correctly in both directions — electrical to optical, optical to electrical — and how are you going to root-cause problems when the system is not working? We will need to gather key information as early as possible to determine what causes data transmission issues.
Source: Semiconductor Engineering Chips and Packaging · semiengineering.com