Reducing Lithography Learning Cycles To Accelerate FOPLP Ramps

For manufacturers scaling advanced AI packages, pressure is mounting from every direction.

On one side, demand continues to rise.

While on another, AI packages are growing larger and integrating more high-bandwidth memory (HBM) and high-performance chips.

And that’s to say nothing of the production teams who face increasing pressure to ramp new processes quickly.

While achieving high yield remains a critical goal, success increasingly depends on how quickly manufacturers can establish stable process conditions and transition from development to high-volume manufacturing (HVM).

Fan-out panel-level packaging (FOPLP) has emerged as an attractive path forward for manufacturers looking to scale advanced packaging production.

Compared with traditional wafer-based approaches, FOPLP can significantly improve substrate utilization while increasing the number of packages produced per substrate. In one study comparison, a 300mm wafer achieved approximately 55% substrate utilization with six packages per wafer, while a 300mm panel achieved 86% utilization with 12 packages per panel and a 510 × 515mm panel achieved 74% utilization with 30 packages per panel. This enables manufacturers to improve manufacturing efficiency and reduce costs per package.

However, realizing those benefits requires overcoming significant lithography challenges.

As panel sizes increase, manufacturers must contend with pattern distortion, die shift, and resulting overlay errors across the substrate. These effects directly impact yield and make process optimization substantially more difficult.

Unlike traditional wafer-based processes, panel-scale variation does not behave uniformly. Instead, distortion patterns can vary significantly across the panel, creating localized challenges that are difficult to correct using conventional approaches.

The sweet spot

Ultimately, process engineers must identify the “sweet spot” between overlay yield and throughput. To compensate for panel-level distortion, manufacturers typically rely on a range of correction strategies.

Global correction maintains throughput but often leaves localized overlay errors uncorrected. Zone correction can improve yield, with field data in our study indicating yields between 40% and 80%, but at reduced throughput. Die-by-die correction can further improve yield but introduces a significant throughput penalty. Site-by-site correction offers a compromise, balancing yield improvement with higher throughput.

However, finding that balance is rarely straightforward.

Identifying the optimal operating window often requires repeated experimentation across variables, such as exposure field configurations, die layouts, panel layouts, and overlay thresholds. Each adjustment can require another trial run and another round of data analysis. The result is increased engineering effort, additional material consumption, longer development cycles, and delayed production ramps.

For manufacturers under pressure to bring capacity online quickly, every additional iteration delays the path to production.

Moving beyond trial-and-error

By combining offline metrology data with yield prediction algorithms, manufacturers can evaluate process performance before committing to extensive physical trials. Instead of repeatedly testing possible operating conditions on production hardware, engineering teams can assess likely yield outcomes in advance and identify promising process windows earlier in the development cycle.

The process begins with detailed metrology measurements that capture panel-scale variation, including pattern errors and die shifts. Yield prediction algorithms then evaluate this information alongside process variables, such as exposure field configuration, panel layout, die layout, and overlay thresholds. Using these inputs, manufacturers can estimate expected yield performance and compare alternative process strategies without executing full production experiments.

The value extends beyond simple prediction. Visualization tools such as heat maps, vector plots, histograms, and yield dashboards help engineers understand process sensitivities, isolate sources of variation, and identify root causes more quickly (Figure 1). This enables more targeted process optimization and faster decision making.

Fig. 1: Yield prediction analysis tools showing 1) parameters for analysis, 2) X-axis overlay error and 3) Y-axis overlay error. A comparison of these maps reveals that the Y-axis exhibits the most significant overlay errors, which directly contribute to yield loss. This insight enables users to pinpoint the root cause of the issue and take corrective actions effectively, thereby improving overall process performance.

Yield prediction technology has also been evaluated using production substrates in an HVM process. In the initial assessment, differences between predicted and measured yield ranged from 1.2% to 2.7%. Further analysis showed that variability in manual inspection judgments was the primary source of the discrepancies. After the inspection process was standardized, prediction errors were reduced to 0.2% to 0.8%.

Accelerating qualification

During process development, manufacturers can use yield prediction technology to evaluate process conditions through simulation before running qualification substrates (Figure 2). Rather than relying exclusively on physical experimentation, engineers can evaluate multiple parameter combinations, identify promising operating conditions, and then use qualification substrates to validate the predictions. This approach can reduce trial-and-error iterations while accelerating process refinement and shortening development timelines.

Fig. 2: Residual overlay error vector maps generated under various process conditions help accelerate process refinement, reduce trial-and-error iterations and improve efficiency during R&D.

Just as important, it helps engineering teams focus their efforts on optimization rather than repetitive trial-and-error experimentation.

Extending yield prediction to mass production

The benefits of yield prediction technology can also extend beyond process development. In mass production, the technology can be integrated into the lithography workflow for real-time, in-line process monitoring and earlier defect detection.

A standard lithography workflow includes multiple process steps before final inspection determines overlay yield. Errors introduced along the way can result in rework or permanent yield loss. By integrating yield prediction earlier in the workflow, manufacturers can identify potential problems before final inspection, enabling earlier intervention while reducing the manpower, time and costs associated with rework (Figure 3).

Fig. 3: Yield prediction technology can be integrated into the production workflow to support real-time, in-line process monitoring and earlier defect detection.

This extends the role of yield prediction from accelerating process development to supporting process monitoring and early defect detection during mass production.

Conclusion

As demand for advanced AI packages continues to rise, manufacturers face growing pressure to establish stable processes, protect yield, and move from development to HVM more quickly. FOPLP offers compelling economic advantages, but pattern distortion, die shift, and yield/throughput tradeoffs can lengthen process learning cycles and delay production ramps.

Yield prediction technology gives manufacturers a way to address these challenges from process development through mass production. During development, this technology can reduce trial-and-error iterations and accelerate process refinement. In mass production, real-time, in-line monitoring can support earlier defect detection and intervention. By incorporating these capabilities into their FOPLP lithography strategies, manufacturers can spend less time finding the right process conditions and advance more efficiently toward stable, high-yield production.