Accelerating Plug-And-Play Prototyping In Chiplet-Based Designs

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With the introduction of multi-die assembly, shared resources, and tools running at different speeds, chip verification has become significantly harder, and simulation alone is no longer enough—simulation, emulation, and FPGA prototyping must be combined to ensure systems work as intended. SignatureIP CEO Purna Mohanty discusses the impact of chiplets and shared memory resources, the version-control challenges of multiple I/O versions, and the engineering challenges that arise when hardware acceleration tools do not match real design speeds.

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Shared resources, a mix of tools running at different speeds, and multiple dies are adding new challenges for design teams.

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Verifying chips is becoming much more difficult in multi-die assemblies. Unlike in the past, when simulation was sufficient, designs now require a combination of simulation, emulation, and FPGA prototyping to ensure that entire systems will work as expected. Purna Mohanty, CEO of SignatureIP, talks about the impact of chiplets and shared memory resources, the challenges of version control across multiple flavors of I/O, and the challenges engineering teams face when hardware-accelerated tools are running at different speeds than the actual design.

Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.