Prototyping Verification Challenges in Chiplet Design
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Semiconductor Engineering reported on November 4, 2026 that verification difficulties in chiplet (multi-die) design are rising significantly. The report notes that with the introduction of multi-die assembly, shared resources, and tools running at different speeds, simulation alone is no longer sufficient to ensure the system works as intended; verification requires combining simulation, emulation, and FPGA prototyping. In an interview, SignatureIP CEO Purna Mohanty discussed several major engineering challenges in this field: the added verification complexity from chiplets and shared memory resources, version control difficulties with multiple I/O versions, and engineering difficulties caused by mismatches between hardware acceleration tools and actual design speeds. The report argues that a plug-and-play prototyping approach can help accelerate verification in multi-die designs. This is currently the only report on this event, with no further developments.
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- Semiconductor Engineering Chips and PackagingAccelerating Plug-And-Play Prototyping In Chiplet-Based Designs
With the introduction of multi-die assembly, shared resources, and tools running at different speeds, chip verification has become significantly harder, and simulation alone is no longer enough—simulation, emulation, and FPGA prototyping must be combined to ensure systems work as intended. SignatureIP CEO Purna Mohanty discusses the impact of chiplets and shared memory resources, the version-control challenges of multiple I/O versions, and the engineering challenges that arise when hardware acceleration tools do not match real design speeds.
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