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#Applied Materials

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TodayOct 22Thu
  1. Semiconductor Engineering Chips and Packaging36

    Beyond The EPE Budget: Building The Next Generation Of Computational Lithography

    At the SPIE Photomask and EUV Lithography conference, a panel of experts from IBM, Carl Zeiss SMT, Micron, ASML, Tekscend and Applied Materials said edge placement error (EPE) has risen from a single lithography metric to a system-level problem, with contributions from masks, scanners, photoresist, etch, metrology and OPC.

Oct 9Fri
  1. Semiconductor Engineering Chips and Packaging26

    Chip Industry Week In Review

    TSMC and GlobalFoundries signed a $2 billion agreement under which GlobalFoundries will manufacture silicon interposers for TSMC's CoWoS advanced packaging ecosystem at its Malta, New York plant, with volume production ramping in the first half of 2028.