Agentic AI Explores Heterogeneous Chip and Interconnect Architectures (Argonne, UIUC)
Agentic AI Explores Heterogeneous Chip and Interconnect Architectures (Argonne, UIUC)
Argonne National Laboratory and the University of Illinois Urbana-Champaign published a paper proposing ArchAgent, a hierarchical multi-agent framework that uses an LLM-based planner to decompose heterogeneous system design into three subproblems—chip, scale-up, and scale-out—each handled by specialized agents.
Researchers at Argonne National Laboratory and the University of Illinois Urbana-Champaign published a technical paper titled “Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains.”
Abstract Excerpt:
“The design space of modern AI/HPC systems has expanded rapidly across compute architectures, including GPUs, dataflow processors, and RISC-V accelerators; memory technologies, including HBM, GDDR, and SRAM; and interconnects such as NVLink, UALink, Infinity Fabric, InfiniBand, Slingshot, and Ultra Ethernet. No single architecture is optimal across LLM training, LLM serving, and AI-coupled HPC workloads, while the resulting combinatorial design space is too large for manual exploration. We present ArchAgent, a hierarchical multi- agent framework in which an LLM-based planner decomposes system design into chip, scale-up, and scale-out subproblems, each handled by specialist agents.”
Find the technical paper here. October 2026.
Emani, Murali, and Kashyap Manjusha. “ArchAgent: Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains.” arXiv preprint arXiv:2610.23724 (October 2026). https://doi.org/10.48550/arXiv.2610.23724. License.
Source: Semiconductor Engineering Chips and Packaging · semiengineering.com