Breaking The Memory Bottleneck In AI And HPC SoCs
Breaking The Memory Bottleneck In AI And HPC SoCs
Embedded memory, not compute, is becoming the bottleneck in AI and HPC SoCs, accounting for over half of chip area. A Synopsys white paper analyzes how GAA devices and backside power delivery (BSPDN) change embedded memory requirements, and presents silicon-measured results from SRAM and register file test chips on Intel 18A: 5–10% density gains and up to about 4% ISO-power performance gains.
Opimizing embedded memory IP for RibbonFET and PowerVia.
Embedded memory, not compute, has become the limiting factor in AI and HPC SoCs, consuming more than half of total die area while constraining bandwidth, latency, and energy efficiency. As the industry transitions to gate-all-around (GAA) devices and backside power delivery network (BSPDN) technology, embedded memory architectures must evolve to keep pace.
This white paper examines how these shifts redefine embedded memory requirements and how Synopsys Embedded Memory IP addresses them through device-aware architectures, power-optimized designs, and highly configurable compilers. It also presents silicon results from SRAM and Register File test chips on the Intel 18A process node, including density improvements in the 5–10% range and ISO-power performance gains of up to approximately 4%.
Read the paper to discover how RibbonFET and PowerVia enable PPA improvements and reduce advanced-node integration risk.
What you’ll learn:
- Why embedded memory, not compute, is limiting AI and HPC SoC performance
- How GAA devices and BSPDN technology reshape advanced-node embedded memory
- The critical PPA, power-delivery, and configurability requirements for embedded memory IP
- How RibbonFET and PowerVia enable measurable PPA improvements
- What silicon-proven SRAM and Register File results show on Intel 18A
To read more, click here.
Source: Semiconductor Engineering Chips and Packaging · semiengineering.com