Synopsys Releases Intel 18A Embedded Memory IP White Paper
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On October 19, 2026, Semiconductor Engineering reported that Synopsys released a white paper focused on the memory bottleneck problem in AI and HPC SoCs. The white paper states that embedded memory, rather than compute, is becoming the bottleneck in AI and HPC SoCs, accounting for more than half of chip area. The white paper analyzes how GAA devices and backside power delivery (BSPDN) technology are changing the design requirements for embedded memory, and presents measured results from SRAM and Register File test chips on the Intel 18A process: density improved by 5–10%, and ISO-power performance improved by up to about 4%. The event is currently at the stage of the white paper release and technical interpretation.
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- Semiconductor Engineering Chips and PackagingBreaking The Memory Bottleneck In AI And HPC SoCs
Embedded memory, not compute, is becoming the bottleneck in AI and HPC SoCs, accounting for over half of chip area. A Synopsys white paper analyzes how GAA devices and backside power delivery (BSPDN) change embedded memory requirements, and presents silicon-measured results from SRAM and register file test chips on Intel 18A: 5–10% density gains and up to about 4% ISO-power performance gains.
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