Which Passing Chips Need More Testing?

Key Takeaways:

• Chips that pass identical tests can carry very different reliability risks, because marginal behavior often hides inside specification limits.
• Device-level models, cross-insertion data, and physical inspection can flag suspicious passing parts, but an anomaly isn’t proof of a defect.
• Extra screening pays off only when the added test can expose the suspected weakness at a lower cost than the failures it may prevent.

A chip passes wafer sort, moves through assembly, and passes final test. Nothing in its results gives anyone a reason to hold it. Yet another chip with nearly identical results could fail in the field because of a weakness neither test exposed, whether that’s a thin timing margin, a slight resistance shift, or a combination of measurements that looks harmless when each is viewed alone.

The challenge for manufacturers is figuring out which of those passing chips deserve another look without retesting everything. Test engineers have always known that a passing result doesn’t guarantee lifetime reliability. What’s changed is how much they can learn about each device. Internal parametric measurements, manufacturing history, and predictive models can now reveal unusual behavior inside a population of passing parts, but spotting a suspicious device is just the beginning.

“The cost of test and the amount of test is exploding, and the ability to test before system-level test is a challenge,” said Kimon Michaels, executive vice president of products and solutions, director, and co-founder of PDF Solutions. “But of course, one of the big challenges is how much of your supply chain is at risk at that point, or the amount of product that you’re throwing away if it fails at that point.”

The longer a marginal device goes undetected, the more value gets invested in it. But testing every device more thoroughly isn’t free. Extra patterns eat tester time, burn-in ties up equipment, a packaged device may need another mechanical insertion, and rejecting every statistical outlier throws away some good silicon. On the other side of the ledger is the part that escapes into a customer’s system.

“Nothing is more expensive than a field failure,” said Michaels. “The challenge is the advanced technologies, in some respects, are even more sensitive to reliability failures.”

Manufacturing tests can only approximate the conditions a chip will see in operation. Voltage, temperature, timing, and workload are controllable during test, but the interactions inside a fully assembled system are much harder to reproduce.

“Individual dies can pass wafer sort and final test, and then behave differently once the dies, memory devices, interconnects, firmware, and software are all working together,” said Eli Roth, smart manufacturing product manager at Teradyne. “We’re very good at finding hard failures. What’s much harder is finding devices that meet spec but are operating close to a reliability boundary.”

Testing every combination of operating conditions is impractical, and even extensive system-level tests cannot guarantee that every weakness will surface. Manufacturers need a way to identify high-risk devices and decide whether a targeted test can expose the problem before shipment.

Device-level models are exposing hidden outliers
Conventional production testing relies on defined limits, with guard-bands for measurement uncertainty and operating variation. Statistical analysis can flag devices near those limits or behaving differently from their neighbors on the same wafer or lot. Nevertheless, a chip can still pass every test while showing an unusual relationship among its measurements.

Device-specific models offer another way to identify those differences. By comparing internal parametric measurements with the behavior expected from a particular device, engineers can detect inconsistencies that population-based statistics might overlook. Process and timing signatures can provide the basis for predicting how a chip should behave, allowing engineers to investigate discrepancies between predicted and measured performance. The pattern of those discrepancies matters. Design-related margin limits tend to show up consistently across a product population, but material problems don’t.

“Material-induced variability behaves differently. It is often localized, asymmetric, or statistically scattered,” said Nir Sever, senior director of business development at proteanTecs. “Only a subset of devices, wafers, or regions on a die may show accelerated drift. The degradation slope may diverge from the population over time.”

Localized or accelerating changes can suggest an emerging physical weakness. The difficulty is determining whether that variation represents a reliability risk worth investigating, and whether another test can reveal anything useful about it. The models making those calls also have a shelf life.

“Data is not static,” said Michaels. “It drifts. It’s physics-based. There are changes to the process, and you have to be cognizant of that in how you retrain, how you monitor, etc.”

Process adjustments, equipment changes, and product revisions can alter the relationships a model learned. That means engineers need to validate the models as carefully as the measurements feeding them, especially when an outlier flag can trigger extra screening or reject a part.

Inspection is explaining marginal electrical behavior
Some latent defects don’t produce a consistent electrical failure. A weakened interconnect may conduct well enough at room temperature, then become unstable under thermal or mechanical stress. That’s particularly hard to catch in advanced packages. Partial non-wetting, micro-bump voids, delamination, and warpage may not cause an immediate failure.

“Voiding and non-wetting may weaken an interconnect without causing an immediate open,” said Chris Rand, principal technical engineer at Nordson Test & Inspection. “Variation in bump height, solder volume, or interconnect geometry can shift resistance or create continuity that changes under load, temperature, or handling.”

X-ray or acoustic inspection can provide physical evidence of a suspected interconnect problem, while electrical measurements help establish whether an observed irregularity affects device behavior. Neither technique necessarily provides a complete diagnosis on its own. Correlating the results can narrow the possible failure mechanisms and help engineers select a stress condition more likely to expose the weakness.

Comparing measurements across test insertions offers another clue. A chip may pass at every stage while its electrical characteristics slowly shift, a trend that individual pass/fail decisions would miss.

“An unexplained drift is not a healthy sign,” said Greg Prewitt, director of Exensio Solutions at PDF Solutions. “If a device just changes, and you don’t think it’s a problem with the test setup, it requires more scrutiny.”

Flagging that device and carrying the flag to later insertions lets manufacturers focus extra screening on parts with suspicious histories. But engineers first have to rule out differences in temperature, calibration, contact resistance, or instrument configuration. Otherwise, they risk chasing a healthy device while missing a problem in the measurement path.

Failure mechanisms are determining which test comes next
Once the evidence points to a credible failure mechanism, the question becomes which additional test has a reasonable chance of exposing it. The options aren’t interchangeable. Suspicious timing may call for characterization at a different voltage or temperature. An interconnect concern may need electrical or thermal stress, while a reliability-risk signature may justify burn-in. Repeating the original test under the same conditions adds little if that test was never sensitive to the defect in the first place.

Burn-in is a particularly tough call. Elevated temperature and voltage can accelerate certain failure mechanisms, but the process consumes equipment time, power, and capacity, and the stress itself can affect reliability. That makes blanket burn-in hard to justify when only a small fraction of passing devices are at risk.

“People are burning in large fractions of their inventory, or nearly all of it, which is expensive and can cause damage by itself,” said Michaels. “But a fairly broad model can learn the insights as to what multi-dimensional part of your process-based plus your test state predicts, and what the sweet spot is where you can skip it and focus your resources on the more marginal parts where you have concern.”

Predictive burn-in uses manufacturing history and test data to identify devices most likely to benefit from stress screening. Adaptive test takes a related approach, using wafer-level and die-level results to determine how a device should be tested after assembly. Information gathered at one insertion can influence the limits and patterns used at the next, provided the manufacturer can preserve device identity and connect the results across operations.

”We have established a kind of cloud infrastructure that is fetching data from the different test insertions and reusing the data collected at earlier test insertions to optimize the die matching inside advanced packaging, the test conditions and consequently the yield for the following test insertions,” said Fabio Pizza, test technology director at Advantest. “You can have a kind of adaptive test to make sure that when you test the device after assembly, you are using the right limits and even the right pattern.”

Changing limits or patterns within an existing insertion generally imposes less overhead than routing a packaged device through another operation, which adds handling, equipment demands, and time. The economics become more complicated as additional value is invested in each device. An extra test may be inexpensive compared with scrapping an assembled multi-die package, but every added operation competes for finite manufacturing capacity.

“When you look at the economics, test costs are dwarfed by scrap costs once you start packaging these devices together,” said Teradyne’s Roth.

The challenge is deciding where that additional screening produces enough value to justify its cost. Connecting wafer, assembly, and final-test results can help engineers identify suspicious devices before more manufacturing value is added, while avoiding test operations that contribute little useful information. A few seconds of targeted screening may prevent an expensive downstream failure, but an extra insertion that rarely finds anything can reduce throughput without improving outgoing quality.

Retesting is creating its own uncertainty
Retesting has an obvious appeal. If engineers don’t trust a result, another measurement seems like cheap insurance. But production test involves physical interfaces, and those interfaces aren’t passive. Packaged devices are pressed into sockets with substantial force to make contact across hundreds or thousands of terminals. Contacts wear, surfaces get contaminated, and small seating variations change resistance, so a second insertion may not reproduce the conditions of the first even when the test program is identical.

“Every time you put that part into the socket, there’s risk involved,” said Jack Lewis, chief technologist at Modus Test. “So retest is a problem. You don’t want to be retesting. Test times are long.”

Repeated insertions consume capacity and expose the package to more handling. If the underlying issue is contact-related, a second test may produce a different result without explaining which measurement better reflects the device. A pass after an earlier fail is especially ambiguous. The device may have been healthy all along, with the original failure caused by poor contact, or it may carry an intermittent defect that simply didn’t show up the second time. Changing the bin without keeping the history throws away the information needed to tell those cases apart.

Comparing results across probe pins, boards, and testers can help establish whether a failure belongs to the device or the measurement system. That requires more than routine calibration, particularly when a tester resource or load-board component begins drifting toward its operating limits.

“Customers also want to do some dedicated measurements to monitor if there is any parameter of the complete test cell that is deviating, if there is any resource in the tester, load board, probe card or thermal control system that is going closer to the limit and potentially creating some marginalities when testing such devices,” said Advantest’s Pizza.

Monitoring tester and load-board performance helps engineers distinguish changes in the measurement environment from changes in the silicon. That history becomes particularly valuable when deciding whether a previously passing device needs more screening, because another insertion may reproduce the symptom without identifying its cause. In that case, other evidence has already raised the possibility of latent risk, so the added insertion should have a real chance of revealing the suspected defect, particularly when the part is expensive or a field failure would be severe. A method that catches more marginal devices but sharply increases false rejects, handling damage, or tester occupancy may not be worth it.

Decision latency is limiting what screening can catch
Even a good screening model fails operationally if its answer arrives too late. Some production test operations are completed in fractions of a second, and an analysis completed after the lot has moved on may help future process improvements without changing the disposition of the parts that generated the data.

Historically, test systems have been optimized to maintain throughput, sometimes at the expense of immediate data availability. Roth described an IDM customer whose test infrastructure deliberately deferred building its test data files until the tester had idle time. That approach kept production moving, but it also limited opportunities to respond to problems as they emerged.

“In extreme cases, STDF files aren’t built until the end of a lot,” said Roth. “So if something goes wrong on an early wafer, we’re not collecting or presenting that data in time for anyone to act on it. Historically, that’s been the trade-off in the push for throughput.”

Getting information sooner is only part of the problem. Data must be tied to the correct device, available in usable form, and delivered while the test program or manufacturing system can still respond. Enabling an extra measurement within the current test sequence may be relatively straightforward. Routing a device to another operation, placing it on hold, or evaluating it against data from elsewhere in the flow is more complicated.

The rules governing those actions need attention, too. If a model starts flagging a growing share of passing devices, engineers have to determine whether the process changed, the devices became more marginal, or the model drifted. Automatically ramping up screening in response could consume test capacity without improving quality. The reverse risk applies when a model learns that a particular test rarely finds defects and recommends running it less often.

Establishing a reliable baseline becomes especially difficult with new chip designs. Complex devices generate enormous amounts of measurement data, but engineers may have little historical information against which to judge an unusual result. Without a dependable reference, even a sophisticated model can struggle to distinguish a meaningful anomaly from normal variation.

“Being able to accurately, empirically assess the data and find out what’s anomalous and what’s not is by no means an easy task,” said Brent Bullock, test technology director at Advantest. “Engineers may not have reliable historical data for comparison, particularly when testing a new chip design or moving to a different architecture.”

A screening model needs to establish what constitutes normal behavior for the device and operating conditions being evaluated. That baseline must remain valid as manufacturing processes, product revisions, and test conditions change. Otherwise, engineers risk increasing test coverage in response to harmless variation or reducing coverage when a genuine weakness is developing.

Engineers also need to know why a device was selected, what evidence triggered the decision, what the extra test found, and whether the result supported the original risk assessment. Without that feedback loop, manufacturers accumulate screening rules that are expensive to maintain and hard to justify. With it, they can judge screening by actual outcomes rather than by the apparent sophistication of the model.

Conclusion
The decision to release a marginal device comes down to what manufacturers can establish about it and how much uncertainty they’re willing to accept. Flagging a component as at risk isn’t the same as predicting failure. A risk score may justify further characterization, a different stress condition, or closer monitoring of a population, but it doesn’t automatically justify scrapping the part. Some failure mechanisms also remain hard to reproduce under practical production conditions, so even a well-chosen test may reduce uncertainty without eliminating it.

The calculation also varies by market. A supplier of high-volume consumer devices may accept a different balance of test cost and residual risk than one serving automotive, industrial, or other high-reliability applications. Even within a product family, the right response depends on how severe the suspected failure mechanism is and how well the available screening methods can expose it.

As more data becomes available about each device, the hard question is shifting from whether a manufacturer can take another measurement to whether that measurement is likely to change the outcome. Manufacturers have spent decades getting better at determining whether a chip passes. Now they also have to decide which passing chips deserve another look, and when the evidence is strong enough to leave them alone. The better they get at that, the less extra testing they may need.

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